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74ACT11821 PDF预览

74ACT11821

更新时间： 2024-11-21 12:50:35
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
7页 124K
描述
10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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中文翻译

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74ACT11821 数据手册

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SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993  
54ACT11821 . . . JT PACKAGE  
74ACT11821 . . . DW PACKAGE  
• Inputs Are TTL-Voltage Compatible  
• Provides Extra Data Width Necessary for  
Wider Address/Data Paths or Buses With  
Parity  
(TOP VIEW)  
1Q  
2Q  
3Q  
OE  
1D  
2D  
1
28  
27  
26  
• Flow-Through Architecture Optimizes  
2
PCB Layout  
3
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
4Q  
5Q  
4
25 3D  
CC  
5
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
4D  
5D  
V
6
GND  
GND  
GND  
GND  
6Q  
7Q  
8Q  
9Q  
10Q  
• EPIC(Enhanced-Performance Implanted  
7
CMOS) 1-µm Process  
CC  
8
V
CC  
• 500-mA Typical Latch-Up Immunity at 125°C  
9
6D  
7D  
8D  
9D  
10D  
CLK  
• Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Ceramic 300-mil  
DIPs  
10  
11  
12  
13  
14  
description  
These 10-bit flip-flops feature 3-state outputs  
designed specifically for driving highly-capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
54ACT11821 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2 1 28 27 26  
5
6
7
8
9
On the positive transition of the clock the Q outputs  
will follow the D inputs.  
2D  
1D  
OE  
1Q  
2Q  
3Q  
4Q  
25 8D  
24 9D  
10  
23  
22  
21  
20  
19  
A buffered output enable (OE) input can be used  
to place the ten outputs in either a normal logic  
state (high or low level) or a high-impedance state.  
In the high-impedance state the outputs neither  
load nor drive the bus lines significantly.  
CLK  
10Q  
9Q  
10  
8Q  
11  
12 13 14 15 16 17 18  
The high-impedance state and increased drive  
provide the capability to drive the bus lines in a  
bus-organized system without need for interface  
or pull-up components.  
The output enable (OE)does not affect the internal operation of the flip-flops. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The 54ACT11821 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
74ACT11821 is characterized for operation form −40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
1234567

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与74ACT11821相关器件

型号 品牌 获取价格 描述 数据表
74ACT11821D PHILIPS

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 		D Flip-Flop, 10-Func, Positive Edge Triggered, CMOS, PDSO28
74ACT11821D-T YAGEO

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 		暂无描述
74ACT11821DW ROCHESTER

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 		ACT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO28, PLASTIC, SO-28
74ACT11821DW TI

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 		10-Bit Bus Interface Flip-Flops with 3-State Outputs 28-SOIC -40 to 85
74ACT11821DWR TI

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 		10-Bit Bus Interface Flip-Flops with 3-State Outputs 28-SOIC -40 to 85
74ACT11821J TI

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 		IC,FLIP-FLOP,10-BIT,D TYPE,ACT-CMOS,DIP,28PIN,CERAMIC
74ACT11821N YAGEO

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 		Bus Driver, ACT Series, 1-Func, 10-Bit, True Output, CMOS, PDIP28
74ACT11821N TI

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 		IC,FLIP-FLOP,10-BIT,D TYPE,ACT-CMOS,DIP,28PIN,PLASTIC
74ACT11821NT TI

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 		10-Bit Bus Interface Flip-Flops with 3-State Outputs 28-PDIP -40 to 85
74ACT11824D YAGEO

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 		Bus Driver, ACT Series, 1-Func, 9-Bit, Inverted Output, CMOS, PDSO28

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