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74ACT11800DWR PDF预览

74ACT11800DWR

更新时间： 2024-11-18 20:08:03
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
5页 81K
描述
ACT SERIES, TRIPLE 4-INPUT AND/NAND GATE, PDSO24, PLASTIC, SO-24

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74ACT11800DWR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：ACT
JESD-30 代码：R-PDSO-G24长度：15.4 mm
逻辑集成电路类型：AND/NAND GATE功能数量：3
输入次数：4端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified座面最大高度：2.65 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

74ACT11800DWR 数据手册

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54ACT11800, 74ACT11800  
TRIPLE 4–INPUT AND/NAND GATES  
SCAS245 – JULY 1990 – REVISED AUGUST 1992  
54ACT11800 . . . JT PACKAGE  
74ACT11800 . . . DW OR NT PACKAGE  
(TOP VIEW)  
• Inputs Are TTL-Voltage Compatible  
• Less Than 0.5 ns Skew Between True and  
Complementary Outputs  
• Suitable for Use in Applications Such As:  
– Differential Line Drivers  
1A  
1Y  
1Z  
1B  
1C  
1D  
2A  
2B  
V
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
– Complementary Input Circuits for  
Decoders and Code Converters  
– Symmetrical Complementary Clock  
Generators  
3
2Y  
4
GND  
GND  
GND  
GND  
2Z  
3Y  
3Z  
3D  
5
6
CC  
V
• Flow-Through Architecture Optimizes PCB  
7
CC  
2C  
2D  
3A  
3B  
3C  
Layout  
8
9
• Center-Pin V  
and GND Pin Configurations  
Minimize High-Speed Switching Noise  
CC  
10  
11  
12  
• EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
• 500-mA Typical Latch-Up Immunity at 125°C  
54ACT11800 . . . FK PACKAGE  
(TOP VIEW)  
• Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
4
3
2
1
28 27 26  
25  
5
1D  
1C  
1B  
NC  
1A  
1Y  
1Z  
3A  
3B  
3C  
description  
6
24  
23  
The ’ACT11800 is a triple 4-input AND/NAND  
gate. It is designed for symmetrical  
complementary clock-generator applications due  
to the delay time in either function (AND/NAND)  
being typically 4 ns with less than 0.5 ns skew  
between true and complementary outputs.  
Elimination of decode spikes in symmetrical  
decoder and code-converter applications makes  
the device useful for applications such as a  
decoder or differential line driver.  
7
8
22 NC  
21 3D  
20 3Z  
19 3Y  
9
10  
11  
12 13 14 15 16 17 18  
NC–No internal connection  
The 54ACT11800 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
74ACT11800 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
A
L
B
C
X
X
L
D
X
X
X
L
Y
L
L
L
L
H
Z
H
H
H
H
L
X
L
X
X
X
H
X
X
H
X
H
H
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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