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74ACT11825DW PDF预览

74ACT11825DW

更新时间: 2024-01-22 05:31:40
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 109K
描述
8-Bit Bus Interface Flip-Flops with 3-State Outputs 28-SOIC -40 to 85

74ACT11825DW 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP28,.4针数:28
Reach Compliance Code:not_compliant风险等级:5.92
其他特性:WITH TRIPLE OUTPUT ENABLE; WITH CLEAR AND CLOCK ENABLE系列:ACT
JESD-30 代码:R-PDSO-G28长度:17.9 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):12.3 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

74ACT11825DW 数据手册

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74ACT11825  
8-BIT BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS154A – D3715, NOVEMBER 1990 – REVISED APRIL 1993  
DW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Multiple Output Enables Allow Multiuser  
Control of the Interface  
OE1  
1Q  
2Q  
3Q  
4Q  
GND  
GND  
GND  
GND  
5Q  
OE2  
OE3  
1D  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Flow-Through Architecture Optimizes  
2
PCB Layout  
3
2D  
4
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
3D  
5
4D  
6
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
V
7
CC  
V
8
CC  
500-mA Typical Latch-Up Immunity at 125°C  
5D  
9
6D  
7D  
8D  
CLKEN  
CLK  
10  
11  
12  
13  
14  
description  
6Q  
7Q  
8Q  
CLR  
This device contains eight flip-flops that feature  
3-state outputs designed specifically for driving  
highly-capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing multiuser registers, I/O ports,  
bidirectional bus drivers, and working registers.  
Withtheclock-enable(CLKEN)inputlow, theeightedge-triggeredD-type flip-flopsenterdataonthelow-to-high  
transition of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. The 74ACT11825  
has noninverting data (D) inputs. Taking the clear (CLR) input low causes the eight Q outputs to go low  
independently of the clock.  
Multiuser buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either  
a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs  
neither load nor drive the bus lines significantly.  
The high-impedance state and increased drive provide the capability to drive bus lines without need for interface  
or pullup components. The output enable (OE) does not affect the internal operation of the flip-flops. Old data  
can be retained or new data can be entered while the outputs are in the high-impedance state.  
The 74ACT11825 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
OE  
L
CLR CLKEN CLK  
D
X
H
L
L
H
H
H
X
X
L
X
L
L
H
L
L
L
L
H
X
X
X
X
X
Q
0
H
Z
OE = H if any of OE1, OE2, or OE3 are high.  
OE = L if all of OE1, OE2, or OE3 are low.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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