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74ACT11174DW PDF预览

74ACT11174DW

更新时间: 2024-11-08 02:58:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
6页 77K
描述
HEX D-TYPE FLIP-FLOP WITH CLEAR

74ACT11174DW 数据手册

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ꢀ ꢁꢂ ꢃ ꢄꢅꢅꢅꢀ ꢁ  
ꢆꢇꢈ ꢉꢊ ꢋꢄꢌ ꢍꢇꢉ ꢎꢏ ꢐ ꢍꢋꢎ ꢏꢑ ꢍꢉꢒ ꢐ ꢄ ꢆꢉ ꢃ ꢏꢇ ꢂꢓ  
SCAS145 − D3435, MARCH 1990 − REVISED APRIL 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Applications Include: Buffer/Storage  
Registers, Shift Registers, Pattern  
Generators  
1Q  
2Q  
CLR  
1D  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Fully-Buffered Outputs for Maximum  
3Q  
2D  
Isolation From External Disturbances  
GND  
GND  
GND  
GND  
4Q  
3D  
Flow-Through Architecture Optimizes  
V
CC  
PCB Layout  
V
CC  
4D  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
13 5D  
12 6D  
5Q  
EPICt (Enhanced-Performance Implanted  
11  
6Q  
CLK  
CMOS) 1-mm Process  
500-mA Typical Latch-Up Immunity at 125°C  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
description  
This device contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information at  
the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the  
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time  
of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect  
at the output.  
The 74ACT11174 is characterized for operation from − 40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
X
D
X
H
L
L
H
L
H
H
H
L
X
Q
0
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢢ  
Copyright 1993, Texas Instruments Incorporated  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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