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ꢇ ꢈꢂꢉꢊ ꢈꢋꢌ ꢍꢎ ꢉꢏꢄ ꢐꢋꢍ ꢎꢑ ꢌ ꢒꢋꢏ ꢑ ꢌ ꢓ ꢋꢎꢔ ꢒ ꢄ ꢕꢎ ꢃ ꢌꢍ ꢂꢊ
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SCAS089 − D3385, DECEMBER 1989 − REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
• Inputs Are TTL-Voltage Compatible
• Buffered Clock and Direct Clear Inputs
• Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
1Q
2Q
1Q
CLR
1D
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
2Q
• Fully-Buffered Outputs for Maximum
GND
GND
GND
GND
3Q
2D
Isolation From External Disturbances
V
V
CC
CC
• Flow-Through Architecture to Optimize
PCB Layout
3D
4D
• Center-Pin V
and GND Configurations
Minimize High-Speed Switching Noise
CC
3Q
4Q
CLK
4Q
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-
Outline Packages and Standard Plastic
300-mil DIPs
description
This device contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information
at the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of
the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has
no effect at the output.
The 74AC11175 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR
L
CLK
X
D
X
H
L
Q
L
Q
H
L
H
↑
H
L
H
↑
H
H
L
X
Q
Q
0
0
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1993, Texas Instruments Incorporated
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2−1
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