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74ACT11000DRE4 PDF预览

74ACT11000DRE4

更新时间: 2024-11-27 19:57:31
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 384K
描述
Quadruple 2-Input Positive-NAND Gates 16-SOIC -40 to 85

74ACT11000DRE4 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.39其他特性:CENTER PIN VCC AND GND
系列:ACTJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.024 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:12.3 ns
传播延迟(tpd):8.8 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

74ACT11000DRE4 数据手册

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54ACT11000, 74ACT11000  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCAS002A – D2957, JUNE 1987 – REVISED APRIL 1993  
54ACT11000 . . . J PACKAGE  
74ACT11000 . . . D OR N PACKAGE  
Inputs Are TTL-Voltage Compatible  
Flow-Through Architecture Optimizes  
(TOP VIEW)  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
1B  
2A  
2B  
V
1A  
1Y  
2Y  
GND  
GND  
3Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
CC  
V
500-mA Typical Latch-Up Immunity at 125°C  
CC  
3A  
3B  
4A  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and  
Ceramic 300-mil DIPs  
4Y  
4B  
description  
54ACT11000 . . . FK PACKAGE  
(TOP VIEW)  
These devices contain four independent 2-input  
NAND gates. They perform the Boolean functions  
Y = A B or Y = A + B in positive logic.  
The 54ACT11000 is characterized for operation  
over the full military temperature range of – 55°C  
to 125°C. The 74ACT11000 is characterized for  
operation from – 40°C to 85°C.  
3
2
1
20 19  
18  
3B  
4A  
NC  
4B  
4Y  
2A  
1B  
NC  
1A  
1Y  
4
5
6
7
8
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
9 10 11 12 13  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
NC – No internal connection  
X
logic symbol  
logic diagram (positive logic)  
1
1A  
16  
1A  
1Y  
1B  
&
2
3
6
7
1Y  
2Y  
3Y  
4Y  
1B  
15  
2A  
2Y  
2B  
2A  
14  
2B  
11  
3A  
10  
3A  
3Y  
3B  
3B  
9
4A  
8
4A  
4Y  
4B  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74ACT11000DRE4 替代型号

型号 品牌 替代类型 描述 数据表
74ACT11000DE4 TI

完全替代

QUADRUPLE 2-INPUT POSITIVE-NAND GATES
74ACT11000NSR TI

完全替代

Quadruple 2-Input Positive-NAND Gates 16-SO -40 to 85
74ACT11000DR TI

完全替代

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

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