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74ACT11002DR PDF预览

74ACT11002DR

更新时间: 2024-09-16 13:04:51
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
5页 69K
描述
Quadruple 2-Input Positive-NOR Gates 16-SOIC -40 to 85

74ACT11002DR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:SOP, SOP16,.25
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.83其他特性:CENTER PIN VCC AND GND
系列:ACTJESD-30 代码:R-PDSO-G16
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:NOR GATE最大I(ol):0.024 A
功能数量:4输入次数:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:10.6 ns
传播延迟(tpd):8.7 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

74ACT11002DR 数据手册

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54ACT11002, 74ACT11002  
QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
SCAS003A – D2957, JUNE 1987 – REVISED APRIL 1993  
54ACT11002 . . . J PACKAGE  
74ACT11002 . . . D OR N PACKAGE  
Inputs Are TTL-Voltage Compatible  
Flow-Through Architecture to Optimize  
(TOP VIEW)  
PCB Layout  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1A  
1Y  
2Y  
GND  
GND  
3Y  
1B  
2A  
2B  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
V
V
CC  
CC  
500-mA Typical Latch-Up Immunity  
at 125°C  
3A  
3B  
4A  
4Y  
4B  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and  
Ceramic 300-mil DIPs  
54ACT11002 . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain four independent 2-input  
NOR gates. They perform the Boolean functions  
Y = A B or Y = A + B in positive logic.  
3
2
1
20 19  
18  
3B  
4A  
NC  
4B  
4Y  
2A  
1B  
NC  
1A  
1Y  
4
5
6
7
8
The 54ACT11002 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The 74ACT11002 is characterized for  
operation from – 40°C to 85°C.  
17  
16  
15  
14  
9 10 11 12 13  
logic symbol  
1
1  
1A  
1B  
2A  
2B  
3A  
3B  
4A  
4B  
2
3
6
7
16  
15  
14  
11  
10  
9
1Y  
2Y  
3Y  
4Y  
NC – No internal connection  
logic diagram (positive logic)  
1A  
1B  
1Y  
2Y  
3Y  
2A  
2B  
8
3A  
3B  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
4A  
4B  
4Y  
FUNCTION TABLE  
(each gate)  
OUTPUT  
Y
INPUTS  
A
B
X
H
L
H
X
L
L
L
H
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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