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74AC280 PDF预览

74AC280

更新时间: 2024-11-10 22:53:11
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 66K
描述
9 BIT PARITY GENERATOR

74AC280 数据手册

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74AC280  
9 BIT PARITY GENERATOR  
HIGH SPEED:tPD =4 ns (TYP.) atVCC =5V  
LOW POWER DISSIPATION:  
I
CC =4 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
NIH = VNIL =28% VCC (MIN.)  
50TRANSMISSIONLINEDRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 24 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
V
B
M
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
74AC280B  
74AC280M  
Σ
Σ
odd/even parity outputs ( ODD and EVEN). The  
nine data inputs control the output conditions.  
When the number of high level input is odd,  
ODD output is kept high and EVEN output low.  
Conservely, when the output is even, ΣEVEN  
output is kept high and ΣODD low.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 6V  
Σ
Σ
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES280  
IMPROVED LATCH-UP IMMUNITY  
The IC generates either odd or even parity  
making it flexible application.  
The word-length capability is easily expanded by  
cascading.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The AC280 is an advanced high-speed CMOS 9  
BIT PARITY GENERATOR fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology. It is ideal for low  
power applications mantaining high speed  
operation similar to equivalent Bipolar Schottky  
TTL.  
It is composed of nine data inputs (A to I) and  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
December 1998  

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