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74AC280SJX PDF预览

74AC280SJX

更新时间: 2024-11-18 23:24:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 逻辑集成电路光电二极管
页数 文件大小 规格书
6页 68K
描述
Parity Generator/Checker

74AC280SJX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.52
系列:ACJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
逻辑集成电路类型:PARITY GENERATOR/CHECKER湿度敏感等级:1
位数:9功能数量:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3/5 V传播延迟(tpd):18.5 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Arithmetic Circuits最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74AC280SJX 数据手册

 浏览型号74AC280SJX的Datasheet PDF文件第2页浏览型号74AC280SJX的Datasheet PDF文件第3页浏览型号74AC280SJX的Datasheet PDF文件第4页浏览型号74AC280SJX的Datasheet PDF文件第5页浏览型号74AC280SJX的Datasheet PDF文件第6页 
November 1988  
Revised November 1999  
74AC280  
9-Bit Parity Generator/Checker  
General Description  
Features  
The AC280 is a high-speed parity generator/checker that  
accepts nine bits of input data and detects whether an  
even or an odd number of these inputs is HIGH. If an even  
number of inputs is HIGH, the Sum Even output is HIGH. If  
an odd number is HIGH, the Sum Even output is LOW. The  
Sum Odd output is the complement of the Sum Even out-  
put.  
ICC reduced by 50%  
9-bit width for memory applications  
AC280: 5962-92201  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC280SC  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150Narrow Body  
74AC280SJ  
M14D  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Truth Table  
Pin Descriptions  
Number of  
HIGH Inputs  
I0–I8  
Outputs  
Pin Names  
Description  
Data Inputs  
Even  
Odd  
I0I8  
Odd Parity Output  
Even Parity Output  
Ο
Ε
0, 2, 4, 6, 8  
1, 3, 5, 7, 9  
H
L
L
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009955  
www.fairchildsemi.com  

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