Datasheet > 74AC280TTR

74AC280TTR

更新时间： 2024-09-07 23:24:03

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
10页	73K
描述
Parity Generator/Checker

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中文翻译

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数据手册

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74AC280TTR 数据手册

74AC280

9 BIT PARITY GENERATOR

■

HIGH SPEED: t = 6ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 4µA(MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28 % V (MIN.)

50Ω TRANSMISSION LINE DRIVING

CAPABILITY

NIH

NIL

DIP

SOP

TSSOP

T & R

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 24mA (MIN)

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

PLH

PHL

TUBE

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 6V

DIP

SOP

74AC280B

74AC280M

74AC280MTR

74AC280TTR

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 280

IMPROVED LATCH-UP IMMUNITY

TSSOP

Conservely, when the output is even, ΣEVEN

output is kept high and ΣODD low.

DESCRIPTION

The IC generates either odd or even parity making

it flexible application. The word-length capability is

easly expanded by cascading.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

The 74AC280 is an advanced high-speed CMOS

9 BIT PARITY GENERATOR fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS tecnology.

It is composed of nine data inputs (A to I) and odd/

even parity outputs (ΣODD and ΣEVEN). The nine

data inputs control the output conditions. When

the number of high level input is odd, ΣODD

output is kept high and ΣEVEN output low.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2001

1/10

12 3 4 5 6 7...10

中文翻译

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