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74AC138B PDF预览

74AC138B

更新时间: 2024-09-15 22:38:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
10页 278K
描述
3 TO 8 LINE DECODER INVERTING

74AC138B 数据手册

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74AC138  
3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED: t = 4.5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
50TRANSMISSION LINE DRIVING  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
DIP  
SOP  
74AC138B  
74AC138M  
V
CC  
74AC138MTR  
74AC138TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 138  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
or G2B is held high, the decoding function is  
inhibited and all the 8 outputs go to high.  
Tree enable inputs are provided to ease cascade  
connection and application of address decoders  
for memory systems.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74AC138 is an advanced high-speed CMOS  
3 TO 8 LINE DECODER (INVERTING) fabricated  
with sub-micron silicon gate and double-layer  
2
metal wiring C MOS tecnology.  
If the device is enabled, 3 binary select inputs (A,  
B, and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either G2A  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/10  

74AC138B 替代型号

型号 品牌 替代类型 描述 数据表
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