256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
IDT71V65603/Z
IDT71V65803/Z
3.3V I/O, Burst Counter
Pipelined Outputs
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst
mode, the IDT71V65603/5803 can provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/LD signal is
used to load a new external address (ADV/LD = LOW) or increment
the internal burst counter (ADV/LD = HIGH).
Features
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
◆
ZBTTM Feature - No dead cycles between write and read cycles
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control signal
◆
◆
registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
◆
◆
◆
◆
◆
◆
◆
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
Description
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus
cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand
reads. Thus, they have been given the name ZBTTM, or Zero Bus Turn-
around.
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA) .
Pin Description Summary
A
0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1
, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
ZZ
Asynchronous
Synchronous
Static
I/O
0
-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5304 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC-5304/08
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