IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Pipelined Outputs
Commercial and Industrial Temperature Ranges
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
1
0
0
1
0
0
3821 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
3821 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
FunctionalTimingDiagram(1)
n+37
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
CLOCK
(2)
ADDRESS
(A0 - A16)
A37
A37
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
(2)
CONTROL
C37
C37
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q35
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q31
I/O [0:31], I/O P[1:4]
,
NOTE:
3821 drw 03
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
7
6.42