128K x 36, 256K x 18,
IDT71V2557S
IDT71V2559S
IDT71V2557SA
IDT71V2559SA
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter,
Flow-Through Outputs
Features
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it read or write.
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
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The IDT71V2557/59 contain address, data-in and control signal
registers.Theoutputsareflow-through(nooutputdataregister).Output
enable is the only asynchronous signal and can be used to disable the
outputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V2557/59
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite
isinitiated.
The IDT71V2557/59 have an on-chip burst counter. In the burst
mode, the IDT71V2557/59 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst
counter (ADV/LD = HIGH).
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 2.5V (±5%)I/O Supply (VDDQ)
Optional-Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
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Description
TheIDT71V2557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-
bit)synchronousSRAMsorganizedas128Kx36/256Kx18.Theyare
designed to eliminate dead bus cycles when turning the bus around
between reads and writes, or writes and reads. Thus they have been
given the name ZBTTM, or Zero Bus Turnaround.
The IDT71V2557/59 SRAMs utilize IDT's latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball
grid array (BGA) and a 165 fine pitch ball grid array (fBGA).
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andonthenextclockcycletheassociateddatacycleoccurs,be
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE2, CE2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW1, BW2, BW3, BW4
CLK
ADV/LD
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Te s t Data Input
Synchronous
Static
LBO
TMS
Synchronous
Synchronous
N/A
TDI
TCK
Te s t Clo c k
TDO
Test Data Output
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
Data Input / Output
Core Power, I/O Power
Ground
Supply
Supply
VSS
Static
4878 tbl 01
OCTOBER 2004
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©2004IntegratedDeviceTechnology,Inc.
DSC-4878/07