Datasheet > 71V2546S133BQI

71V2546S133BQI

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
25页	220K
描述
ZBT SRAM, 128KX36, 4.2ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

71V2546S133BQI 数据手册

IDT71V2546S/XS

IDT71V2548S/XS

IDT71V2546SA/XSA

IDT71V2548SA/XSA

128K x 36, 256K x 18

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

Features

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andtwocycles latertheassociateddatacycleoccurs,beitread

or write.

◆

128K x 36, 256K x 18 memory configurations

◆

Supports high performance system speed - 150 MHz

(3.8 ns Clock-to-Data Access)

The IDT71V2546/48 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

AClockEnable(CEN)pinallowsoperationoftheIDT71V2546/48to

besuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

◆

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)

Optional Boundary Scan JTAG Interface (IEEE1149.1

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-statetwocyclesafterchipisdeselectedorawriteis

initiated.

◆

complaint)

TheIDT71V2546/48hasanon-chipburstcounter.Intheburstmode,

theIDT71V2546/48canprovidefourcyclesofdataforasingleaddress

presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe

LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V2546/48 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

◆

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array

Description

TheIDT71V2546/48 are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles

when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBT , or Zero Bus

Turnaround.

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE , CE

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

LBO

TMS

TDI

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

Static

5294 tbl 01

MAY 2010

DSC-5294/06

12 3 4 5 6 7...25

中文翻译

下载PDF

与71V2546S133BQI相关器件

型号	品牌	获取价格	描述	数据表
71V2546S133PFG	IDT	获取价格	3.3V Synchronous ZBT SRAM
71V2546S133PFG8	IDT	获取价格	3.3V Synchronous ZBT SRAM
71V2546S133PFGI	IDT	获取价格	3.3V Synchronous ZBT SRAM
71V2546S133PFGI8	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100
71V2546S133PFI8	IDT	获取价格	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQ
71V2546S150BG	IDT	获取价格	PBGA-119, Tray
71V2546S150BGG	IDT	获取价格	3.3V Synchronous ZBT SRAM
71V2546S150BGG8	IDT	获取价格	3.3V Synchronous ZBT SRAM
71V2546S150BGGI	IDT	获取价格	3.3V Synchronous ZBT SRAM
71V2546S150BGGI8	IDT	获取价格	3.3V Synchronous ZBT SRAM

与71V2546S133BQI相关文章

FDG6302P资料解析：电气参数、产品特性
2024-07-01

2
SBAV99WT1G资料手册：参数信息、产品特性、替代型号推荐
2024-07-01

1
MBRS340T3G手册解读：参数说明、产品特性及应用
2024-06-28

8
PMOS管背靠背连接：串联还是并联？
2024-06-28

7

产品中心

服务支持

精选活动

关于我们

帮助中心

71V2546S133BQI

71V2546S133BQI 数据手册

与71V2546S133BQI相关器件

与71V2546S133BQI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

71V2546S133BQI

71V2546S133BQI 数据手册

与71V2546S133BQI相关器件

与71V2546S133BQI相关文章

您还可以找

您在本页遇到什么问题？