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71V016SA12YIG8 PDF预览

71V016SA12YIG8

更新时间: 2024-11-26 14:40:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 85K
描述
Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, PLASTIC, SOJ-44

71V016SA12YIG8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete包装说明:SOJ, SOJ44,.44
Reach Compliance Code:compliant风险等级:5.4
Is Samacsys:N最长访问时间:12 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J44
JESD-609代码:e3内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ44,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大待机电流:0.01 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.16 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
Base Number Matches:1

71V016SA12YIG8 数据手册

 浏览型号71V016SA12YIG8的Datasheet PDF文件第2页浏览型号71V016SA12YIG8的Datasheet PDF文件第3页浏览型号71V016SA12YIG8的Datasheet PDF文件第4页浏览型号71V016SA12YIG8的Datasheet PDF文件第5页浏览型号71V016SA12YIG8的Datasheet PDF文件第6页浏览型号71V016SA12YIG8的Datasheet PDF文件第7页 
3.3V CMOS Static RAM  
1 Meg (64K x 16-Bit)  
IDT71V016SA  
Features  
Description  
64K x 16 advanced high-speed CMOS Static RAM  
TheIDT71V016isa1,048,576-bithigh-speedStaticRAMorganized  
as64Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability  
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-  
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-  
speedmemoryneeds.  
Equal access and cycle times  
— Commercial:10/12/15/20ns  
Industrial:12/15/20ns  
One Chip Select plus one Output Enable pin  
Bidirectional data inputs and outputs directly  
The IDT71V016 has an output enable pin which operates as fast  
as 5ns, with address access times as fast as 10ns. All bidirectional  
inputsandoutputsoftheIDT71V016areLVTTL-compatibleandoperation  
isfromasingle3.3Vsupply.Fullystaticasynchronouscircuitryisused,  
requiringnoclocks orrefreshforoperation.  
LVTTL-compatible  
Low power consumption via chip deselect  
Upper and Lower Byte Enable Pins  
Single 3.3V power supply  
Available in 44-pin Plastic SOJ, 44-pin TSOP, and  
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic  
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.  
48-Ball Plastic FBGA packages  
Functional Block Diagram  
Output  
Enable  
Buffer  
OE  
Address  
Buffers  
Row / Column  
Decoders  
A0 – A15  
I/O15  
High  
Byte  
I/O  
8
8
Chip  
Enable  
Buffer  
CS  
Buffer  
I/O8  
Sense  
Amps  
and  
Write  
Drivers  
16  
64K x 16  
Memory  
Array  
Write  
Enable  
Buffer  
WE  
I/O7  
Low  
Byte  
I/O  
8
8
Buffer  
I/O0  
BHE  
BLE  
Byte  
Enable  
Buffers  
3834 drw 01  
JANUARY 2004  
1
©2004 IntegratedDeviceTechnology,Inc.  
DSC-3834/07  

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