Datasheet > 71P74604S300BQG

71P74604S300BQG

更新时间： 2024-11-06 21:01:27

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
21页	274K
描述
CABGA-165, Tray

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中文翻译

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技术参数
数据手册

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71P74604S300BQG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	CABGA
针数：	165	Reach Compliance Code：	compliant
风险等级：	5.84	JESD-609代码：	e1
内存集成电路类型：	QDR SRAM	湿度敏感等级：	3
峰值回流温度（摄氏度）：	260	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

71P74604S300BQG 数据手册

18Mb Pipelined

QDR™II SRAM

Burst of 4

IDT71P74804

IDT71P74604

Features

Description

The IDT QDRII^TMBurst of four SRAMs are high-speed synchro-

nous memories with independent, double-data-rate (DDR), read and

write data ports. This scheme allows simultaneous read and write

access for the maximum device throughput, with four data items passed

with each read or write. Four data word transfers occur per clock

cycle, providing quad-data-rate (QDR) performance. Comparing this

with standard SRAM common I/O (CIO), single data rate (SDR) de-

vices, a four to one increase in data access is achieved at equivalent

clock speeds. Considering that QDRII allows clock speeds in excess of

standard SRAM devices, the throughput can be increased well beyond

four to one in most applications.

•

18Mb Density (1Mx18, 512kx36)

Separate, Independent Read and Write Data Ports

Supports concurrent transactions

•

Dual Echo Clock Output

4-Word Burst on all SRAM accesses

MultiplexedAddress Bus One Read or One Write request per

clock cycle

•

DDR (Double Data Rate) Data Bus

Four word burst data per two clock cycles on each port

Four word transfers per clock cycle

•

Depth expansion through Control Logic

HSTL (1.5V) inputs that can be scaled to receive signals from

1.4V to 1.9V.

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the QDRII are unidirectional and can be optimized for

signal integrity at very high bus speeds. The QDRII has scalable output

impedance on its data output bus and echo clocks, allowing the user to

tune the bus for low noise and high performance.

The QDRII has a single SDR address bus with read addresses

and write addresses multiplexed. The read and write addresses inter-

leave with each occurring a maximum of every other cycle. In the event

that no operation takes place on a cycle, the subsequest cycle may

begin with either a read or write. During write operations, the writing of

individual bytes may be blocked through the use of byte write control

signals.

•

Scalable output drivers

Can drive HSTL, 1.8V TTL or any voltage level from 1.4V

to 1.9V.

Output Impedance adjustable from 35Ω to 70Ω

•

1.8V Core Voltage (VDD)

165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

JTAG Interface

Functional Block Diagram

(Note1)

DATA

REG

WRITE DRIVER

(Note2)

ADD

REG

(Note 4)

(Note1)

18M

MEMORY

ARRAY

CTRL

LOGIC

(Note3)

BWx

CLK

GEN

SELECT OUTPUT CONTROL

6111 drw16

Notes

1) Represents 18 data signal lines for x18 and 36 signal lines for x36.

2) Represents 18 address signal lines for x18 and 17 address signal lines for x36.

3) Represents 2 signal lines for x18 and 4 signal lines for x36.

4) Represents 36 signal lines for x18 and 72 signal lines for x36.

SEPTEMBER 2008

DSC-6111/02

12 3 4 5 6 7...21

中文翻译

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与71P74604S300BQG相关器件

型号	品牌	获取价格	描述	数据表
71P74604S333BQ	IDT	获取价格	CABGA-165, Tray
71P74804S167BQ	IDT	获取价格	CABGA-165, Tray
71P74804S167BQ8	IDT	获取价格	CABGA-165, Reel
71P74804S167BQG	IDT	获取价格	CABGA-165, Tray
71P74804S167BQG8	IDT	获取价格	CABGA-165, Reel
71P74804S200BQ	IDT	获取价格	CABGA-165, Tray
71P74804S200BQ8	IDT	获取价格	CABGA-165, Reel
71P74804S200BQG	IDT	获取价格	CABGA-165, Tray
71P74804S200BQG8	IDT	获取价格	CABGA-165, Reel
71P74804S250BQ	IDT	获取价格	CABGA-165, Tray

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