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71P74604S167BQG8 PDF预览

71P74604S167BQG8

更新时间： 2024-09-15 21:01:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
21页 274K
描述
CABGA-165, Reel

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71P74604S167BQG8 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：CABGA
包装说明：13 X 15 MM, 1 MM PITCH, GREEN, FBGA-165针数：165
Reach Compliance Code：unknownECCN代码：3A991
HTS代码：8542.32.00.41风险等级：5.84
最长访问时间：0.5 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：167 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：18874368 bit
内存集成电路类型：QDR SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：165字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.3 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：0.85 mA
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

71P74604S167BQG8 数据手册

 浏览型号71P74604S167BQG8的Datasheet PDF文件第2页浏览型号71P74604S167BQG8的Datasheet PDF文件第3页浏览型号71P74604S167BQG8的Datasheet PDF文件第4页浏览型号71P74604S167BQG8的Datasheet PDF文件第5页浏览型号71P74604S167BQG8的Datasheet PDF文件第6页浏览型号71P74604S167BQG8的Datasheet PDF文件第7页 
18Mb Pipelined  
QDR™II SRAM  
Burst of 4  
IDT71P74804  
IDT71P74604  
Features  
Description  
The IDT QDRIITM Burst of four SRAMs are high-speed synchro-  
nous memories with independent, double-data-rate (DDR), read and  
write data ports. This scheme allows simultaneous read and write  
access for the maximum device throughput, with four data items passed  
with each read or write. Four data word transfers occur per clock  
cycle, providing quad-data-rate (QDR) performance. Comparing this  
with standard SRAM common I/O (CIO), single data rate (SDR) de-  
vices, a four to one increase in data access is achieved at equivalent  
clock speeds. Considering that QDRII allows clock speeds in excess of  
standard SRAM devices, the throughput can be increased well beyond  
four to one in most applications.  
•
•
18Mb Density (1Mx18, 512kx36)  
Separate, Independent Read and Write Data Ports  
Supports concurrent transactions  
-
•
•
•
Dual Echo Clock Output  
4-Word Burst on all SRAM accesses  
MultiplexedAddress Bus One Read or One Write request per  
clock cycle  
•
DDR (Double Data Rate) Data Bus  
-
-
Four word burst data per two clock cycles on each port  
Four word transfers per clock cycle  
•
•
Depth expansion through Control Logic  
HSTL (1.5V) inputs that can be scaled to receive signals from  
1.4V to 1.9V.  
Using independent ports for read and write data access, simplifies  
system design by eliminating the need for bi-directional buses. All buses  
associated with the QDRII are unidirectional and can be optimized for  
signal integrity at very high bus speeds. The QDRII has scalable output  
impedance on its data output bus and echo clocks, allowing the user to  
tune the bus for low noise and high performance.  
The QDRII has a single SDR address bus with read addresses  
and write addresses multiplexed. The read and write addresses inter-  
leave with each occurring a maximum of every other cycle. In the event  
that no operation takes place on a cycle, the subsequest cycle may  
begin with either a read or write. During write operations, the writing of  
individual bytes may be blocked through the use of byte write control  
signals.  
•
Scalable output drivers  
-
Can drive HSTL, 1.8V TTL or any voltage level from 1.4V  
to 1.9V.  
-
Output Impedance adjustable from 35Ω to 70Ω  
•
•
•
1.8V Core Voltage (VDD)  
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package  
JTAG Interface  
Functional Block Diagram  
(Note1)  
DATA  
D
REG  
WRITE DRIVER  
(Note2)  
(Note2)  
ADD  
SA  
REG  
(Note 4)  
(Note 4)  
(Note1)  
18M  
MEMORY  
ARRAY  
Q
R
CTRL  
LOGIC  
W
(Note3)  
BWx  
CQ  
K
CLK  
GEN  
K
CQ  
C
SELECT OUTPUT CONTROL  
C
6111 drw16  
Notes  
1) Represents 18 data signal lines for x18 and 36 signal lines for x36.  
2) Represents 18 address signal lines for x18 and 17 address signal lines for x36.  
3) Represents 2 signal lines for x18 and 4 signal lines for x36.  
4) Represents 36 signal lines for x18 and 72 signal lines for x36.  
SEPTEMBER 2008  
1
DSC-6111/02  
©2008 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.  
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