Datasheet > 70V631S15BCGI

70V631S15BCGI

更新时间： 2024-09-11 00:37:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
23页	198K
描述
HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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70V631S15BCGI 数据手册

HIGH-SPEED 3.3V 256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

IDT70V631S

Features

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package.

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 128-pin Thin Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

– Commercial:10/12/15ns(max.)

– Industrial: 12ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V631 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

◆

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Green parts available, see ordering information

Functional Block Diagram

UBL

LBL

R/WR

CE0L

CE0R

CE1L

CE1R

OEL

OER

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

256K x 18

MEMORY

ARRAY

Din_L

I/O0L- I/O17L

Din_R

I/O0R - I/O17R

17R

Address

Decoder

Address

Decoder

17L

ADDR_L

ADDR_R

OER

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE1R

CE0L

CE1L

R/WL

R/WR

BUSY

SEM

INT

M/S

SEM

INT

TMS

TCK

TDI

JTAG

TDO

TRST

5622 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

OCTOBER 2013

DSC-5622/7

12 3 4 5 6 7...23

中文翻译

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与70V631S15BCGI相关器件

型号	品牌	获取价格	描述	数据表
70V631S15BCGI8	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V631S15BFG	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V631S15BFG8	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V631S15BFGI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V631S15BFGI8	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V631S15PRFG	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V631S15PRFG8	IDT	获取价格	Dual-Port SRAM, 256KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, TQFP-128
70V631S15PRFGI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V631S15PRFGI8	IDT	获取价格	HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V639	RENESAS	获取价格	128K x 18 3.3V Dual-Port RAM, Interleaved I/O's

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