HIGH-SPEED 3.3V
128K x 18 ASYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V639S
Features
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
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Fully asynchronous operation from either port
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Separate byte controls for multiplexed bus and bus
matching compatibility
– Commercial:10/12/15ns(max.)
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Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
– Industrial:12/15ns(max.)
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Dual chip enables allow for depth expansion without
external logic
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◆
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LVTTL-compatible, single 3.3V (±150mV) power supply for
core
IDT70V639 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
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On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
Green parts available, see ordering information
between ports
Functional Block Diagram
UB
LB
L
UB
R
L
LB
R
R/WL
R/WR
B
B
E
1
L
B
E
1
B
E
0
E
0
L
CE0L
CE0R
R
R
CE1L
CE1R
OEL
OER
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
128K x 18
MEMORY
ARRAY
Din_L
I/O0L- I/O17L
Din_R
I/O0R - I/O17R
A
A
16R
0R
Address
Decoder
Address
Decoder
A
16L
0L
ADDR_L
ADDR_R
A
OE
L
ARBITRATION
OER
INTERRUPT
SEMAPHORE
LOGIC
CE0R
CE1R
CE0L
CE1L
R/WL
R/WR
BUSY
SEM
INT
R
BUSY
SEM
INT
L
L
M/S
R
L
R
TMS
TCK
TRST
TDI
JTAG
TDO
5621 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JUNE 2015
1
DSC-5621/7
©2015 Integrated Device Technology, Inc.