Datasheet > 70V639S15BFI

70V639S15BFI

更新时间： 2024-09-16 10:43:31

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	185K
描述
Application Specific SRAM, 128KX18, 15ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208

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中文翻译

获取价格

数据手册

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70V639S15BFI 数据手册

HIGH-SPEED 3.3V

128K x 18 ASYNCHRONOUS

DUAL-PORT STATIC RAM

IDT70V639S

Features

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package.

◆

– Commercial:10/12/15ns (max.)

– Industrial:12/15ns (max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V639 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

◆

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 128-pin Thin Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Green parts available, see ordering information

Functional Block Diagram

CE0L

CE0R

CE1L

CE1R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

128K x 18

MEMORY

ARRAY

Din_L

I/O0L- I/O17L

Din_R

I/O0R - I/O17R

16R

Address

Decoder

Address

Decoder

16L

ADDR_L

ADDR_R

OER

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE1R

CE0L

CE1L

R/WL

R/WR

BUSY

SEM

INT

BUSY

SEM

INT

M/S

TMS

TCK

TDI

TDO

JTAG

TRST

5621 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S=V^IL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JANUARY 2009

DSC-5621/6

12 3 4 5 6 7...23

中文翻译

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与70V639S15BFI相关器件

型号	品牌	获取价格	描述	数据表
70V639S15PRF	IDT	获取价格	Application Specific SRAM, 128KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-
70V639S15PRF8	IDT	获取价格	TQFP-128, Reel
70V639S15PRFG	IDT	获取价格	HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V639S15PRFG8	IDT	获取价格	Dual-Port SRAM, 128KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, TQFP-128
70V639S15PRFGI	IDT	获取价格	HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70V639S15PRFGI8	IDT	获取价格	Dual-Port SRAM, 128KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, TQFP-128
70V639S15PRFI	IDT	获取价格	Application Specific SRAM, 128KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-
70V639S15PRFI8	IDT	获取价格	Application Specific SRAM, 128KX18, 15ns, CMOS, PQFP128, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-
70V657	RENESAS	获取价格	32K x 36 3.3V Dual-Port RAM, Interleaved I/O's
70V657S10BCG	IDT	获取价格	HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

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