78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
Transmit Driver
POWER-DOWN FUNCTION
In CMI (electrical) mode, the CMIxP/N pins are
biased and terminated off-chip. They interface to
Power-down controls are provided to allow the
78P2352 to be shut off. Transmit and receive
power-down can be set independently through SW
control. Total power-down is achieved by powering
down both the transmitter and receiver.
75Ω coaxial cable through
a
1:1 wideband
transformer and coaxial RF connectors. Reference
application notes for schematic and layout
guidelines.
Note: The serial interface and configuration
The transmitter encodes the data using CMI line
coding and shapes an analog signal to meet the
appropriate ITU-T G.703 template. The CMI outputs
are tri-stated during transmit disable and transmit
power-down for redundancy applications and power-
savings.
registers are not affected by power-down.
In HW mode, both transmitters can also be globally
powered down using the TXPD control pin.
LOOPBACK MODES
In SW mode, LLBKx and RLBKx bits in the Signal
Control Register are provided to activate the local
and remote loopback modes respectively.
In HW mode, the LPBKx pins can be used to
activate local and remote analog loopback modes as
shown in the table below.
Note: To avoid reflections causing unwanted
board noise, it’s recommended to power-down
unused transmit ports that are not terminated
with cable to an Rx input port.
When the CMI pin is low, the chip is in Fiber
(NRZ pass-through) mode and interfaces directly to
an optical transceiver module. The ECLxP/N pins
are internally biased and output NRZ data at
LVPECL levels. The CMI driver, encoder and
decoder are disabled in Fiber (NRZ) mode.
LPBK pin Analog Loopback Mode
Low
Normal operation
Remote (analog) Loopback:
Recovered receive clock and data
looped back directly to the transmit
driver. The CMI decoder and most of
transmit path is bypassed.
Float
Clock Synthesizer
The transmit clock synthesizer is a low-jitter DLL that
generates a 278.528/311.04 MHz clock for the CMI
encoder. It is also used in both the receive and
transmit sides for clock and data recovery.
Local (analog) Loopback:
High
Transmit clock and data looped back to
receiver at the analog media interface.
This 2x line rate clock is also available at the
TXCKxP/N pins for downstream synchronization or
system debug.
EACH CHANNEL: Tx
Lock Detect
Tx CDR
ECLxP/N
TXxCKP/N
SIxDP/N
FIFO
CMI
Transmit Backplane Equalizer
Encoder
SIxCKP/N
CMIxP/N
An optional fixed LVPECL equalizer is integrated in
the transmit path for architectures that use LIUs on
active interface cards. The fixed equalizer can
compensate for up to 1.5m of FR4 trace and can be
enabled by the TXOUT1 pin or TXEQ bit as follows:
PIxCK
PIx[3:0]D
PTOxCK
PMOD, SMOD[1:0], PAR
RLBK
SOxCKP/N
SOxDP/N
CMI
Rx CDR
Decoder
Adaptive
Eq.
RXxP/N
POx[3:0]D
POxCK
Lock Detect
LOS Detect
CMI
LLBK
TXEQ bit
Tx Equalizer
TXOUT1 pin
EACH CHANNEL: Rx
Low
Float
1
0
Enabled
Disabled
Figure 6: Local (Analog) Loopback
Transmit Loss of Lock
EACH CHANNEL: Tx
Lock Detect
Tx CDR
ECLxP/N
In transmit modes using the integrated CDR, the
78P2352 will declare a loss of lock condition when
there is no valid signal detected at the SIxDP/N data
inputs.
TXxCKP/N
SIxDP/N
FIFO
CMI
Encoder
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PTOxCK
PMOD, SMOD[1:0], PAR
RLBK
Note: The Tx LOL indicator is invalid and
undefined when the parallel (nibble) interface is
selected.
SOxCKP/N
SOxDP/N
CMI
Rx CDR
Decoder
Adaptive
Eq.
RXxP/N
POx[3:0]D
POxCK
Lock Detect
LOS Detect
CMI
LLBK
EACH CHANNEL: Rx
Figure 7: Remote (Analog) Loopback
Page: 7 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
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