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7027L35GB PDF预览

7027L35GB

更新时间: 2024-09-19 15:26:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 161K
描述
Dual-Port SRAM, 32KX16, 55ns, CMOS, CPGA108, 1.210 X 1.210 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-108

7027L35GB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:1.210 X 1.210 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-108
Reach Compliance Code:not_compliant风险等级:5.92
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:S-CPGA-P108JESD-609代码:e0
内存密度:524288 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端口数量:2端子数量:108
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:32KX16
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA108,12X12
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
筛选级别:MIL-PRF-38535最大待机电流:0.01 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.295 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR处于峰值回流温度下的最长时间:30
Base Number Matches:1

7027L35GB 数据手册

 浏览型号7027L35GB的Datasheet PDF文件第2页浏览型号7027L35GB的Datasheet PDF文件第3页浏览型号7027L35GB的Datasheet PDF文件第4页浏览型号7027L35GB的Datasheet PDF文件第5页浏览型号7027L35GB的Datasheet PDF文件第6页浏览型号7027L35GB的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7027S/L  
32K x 16 DUAL-PORT  
STATIC RAM  
Features  
external logic  
True Dual-Ported memory cells which allow simultaneous  
IDT7027 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
access of the same memory location  
High-speed access  
Military: 25/35/55ns (max)  
Industrial: 25ns (max.)  
– Commercial:20/25/35/55ns (max.)  
Low-power operation  
Busy and Interrupt Flags  
On-chip port arbitration logic  
IDT7027S  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin  
Ceramic PinGridArray(PGA)  
Active: 750mW (typ.)  
Standby: 5mW (typ.)  
IDT7027L  
Active: 750mW (typ.)  
Standby: 1mW (typ.)  
Separate upper-byte and lower-byte control for bus  
matching capability.  
Industrial temperature range (40°C to +85°C) is available  
for selected speeds  
Dual chip enables allow for depth expansion without  
FunctionalBlockDiagram  
R/WL  
UBL  
WR  
R/  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
LBR  
OEL  
LBL  
I/O8-15L  
I/O8-15R  
I/O  
Control  
I/O  
Control  
0-7L  
I/O  
I/O0-7R  
(1,2)  
(1,2)  
BUSYR  
BUSYL  
.
32Kx16  
A14R  
A0R  
A14L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
7027  
A0L  
A14L  
A14R  
A0R  
CE0R  
A0L  
CE0L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1L  
OEL  
CE1R  
OER  
WL  
R/  
R/WR  
SEML  
INTL  
SEMR  
(2)  
(2)  
INTR  
M/S(2)  
3199 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
MAY 2000  
1
DSC 3199/7  
©2000IntegratedDeviceTechnology,Inc.  

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