HIGH-SPEED
IDT7027S/L
32K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆
High-speed access
◆
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns (max.)
◆
◆
◆
◆
Busy and Interrupt Flags
Low-power operation
On-chip port arbitration logic
– IDT7027S
Full on-chip hardware support of semaphore signaling
between ports
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
◆
◆
◆
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆
Separate upper-byte and lower-byte control for bus
◆
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
matching capability.
◆
Dual chip enables allow for depth expansion without
external logic
Green parts available, see ordering information
FunctionalBlockDiagram
R/W
L
R/W
R
UB
L
UBR
CE0L
CE0R
CE1L
CE1R
OE
R
OE
LB
L
L
LBR
I/O 8-15L
I/O8-15R
I/O0-7R
I/O
Control
I/O
Control
0-7L
I/O
(1,2)
R
BUSY
BUSY
L
.
32Kx16
14L
A
A
14R
0R
A
Address
Decoder
Address
Decoder
MEMORY
ARRAY
7027
A
0L
A
14L
A
14R
0R
A
CE0R
A
CE0L
0L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE1L
OE
CE1R
OE
L
R
R/W
L
R/WR
SEM
INT
L
L
SEM
R
(2)
(2)
INT
R
M/S(2)
NOTES:
3199 drw 01
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
AUGUST 2015
1
DSC 3199/10
©2015 Integrated Device Technology, Inc.