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70121L20JG8 PDF预览

70121L20JG8

更新时间: 2024-11-12 00:52:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 199K
描述
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

70121L20JG8 数据手册

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HIGH-SPEED  
2K x 9 DUAL-PORT  
IDT70121S/L  
IDT70125S/L  
STATIC RAM  
WITH BUSY & INTERRUPT  
Features  
Fully asychronous operation from either port  
MASTER IDT70121 easily expands data bus width to 18 bits or  
more using SLAVE IDT70125 chip  
On-chip port arbitration logic (IDT70121 only)  
BUSY output flag on Master; BUSY input on Slave  
INT flag for port-to-port communication  
Battery backup operation—2V data retention  
TTL-compatible, signal 5V (±10%) power supply  
Available in 52-pin PLCC  
High-speed access  
– Commercial: 25/35/55ns (max.)  
– Industrial: 35ns (max.)  
Low-power operation  
– IDT70121/70125S  
Active:675mW(typ.)  
Standby: 5mW (typ.)  
– IDT70121/70125L  
Active:675mW(typ.)  
Standby: 1mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
Green parts available, see ordering information  
FunctionalBlockDiagram  
OER  
OEL  
CE  
R/W  
R
CE  
R/W  
L
R
L
I/O0L- I/O8L  
I/O0R-I/O8R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
R
BUSY  
A
10R  
0R  
A
10L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
0L  
11  
11  
ARBITRATION  
INTERRUPT  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
R
OE  
R
R/W  
L
(2)  
(2)  
L
INT  
INTR  
2654 drw 01  
NOTES:  
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.  
70125 (SLAVE): BUSY is input.  
2. INT is non-tri-stated push-pull output.  
AUGUST 2014  
1
DSC 2654/13  
©2014 Integrated Device Technology, Inc.  

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