Datasheet > 70121S45J

70121S45J

更新时间： 2024-11-12 07:22:39

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	194K
描述
Dual-Port SRAM, 2KX9, 45ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52

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中文翻译

获取价格

数据手册

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70121S45J 数据手册

HIGH-SPEED

2K x 9 DUAL-PORT

IDT70121S/L

IDT70125S/L

STATIC RAM

WITH BUSY & INTERRUPT

◆

Features

Fully asychronous operation from either port

MASTER IDT70121 easily expands data bus width to 18 bits or

more using SLAVE IDT70125 chip

On-chip port arbitration logic (IDT70121 only)

BUSY output flag on Master; BUSY input on Slave

INT flag for port-to-port communication

Battery backup operation—2V data retention

TTL-compatible, signal 5V (±10%) power supply

Available in 52-pin PLCC

✵

◆

High-speed access

– Commercial:25/35/45/55ns(max.)

– Industrial: 35ns (max.)

Low-power operation

◆

– IDT70121/70125S

Active:675mW(typ.)

Standby: 5mW (typ.)

– IDT70121/70125L

Active:675mW(typ.)

Standby: 1mW (typ.)

Industrial temperature range (–40°C to +85°C) is available for

selected speeds

Green parts available, see ordering information

◆

FunctionalBlockDiagram

OER

OEL

R/W

I/O0L- I/O8L

I/O0R-I/O8R

I/O

Control

BUSY ^(1,2)

(1,2)

BUSY

10R

10L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

LOGIC

R/W

(2)

INT

INTR

2654 drw 01

NOTES:

1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.

70125 (SLAVE): BUSY is input.

2. INT is non-tri-stated push-pull output.

AUGUST 2014

DSC 2654/12

12 3 4 5 6 7...16

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