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70121L35JGI PDF预览

70121L35JGI

更新时间: 2024-11-11 19:19:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 193K
描述
Dual-Port SRAM, 2KX9, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52

70121L35JGI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QCCJ, LDCC52,.8SQReach Compliance Code:compliant
风险等级:5.24最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J52
JESD-609代码:e3内存密度:18432 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
湿度敏感等级:1功能数量:1
端口数量:2端子数量:52
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2KX9
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC52,.8SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
最大待机电流:0.005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.25 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

70121L35JGI 数据手册

 浏览型号70121L35JGI的Datasheet PDF文件第2页浏览型号70121L35JGI的Datasheet PDF文件第3页浏览型号70121L35JGI的Datasheet PDF文件第4页浏览型号70121L35JGI的Datasheet PDF文件第5页浏览型号70121L35JGI的Datasheet PDF文件第6页浏览型号70121L35JGI的Datasheet PDF文件第7页 
HIGH-SPEED  
2K x 9 DUAL-PORT  
IDT70121S/L  
IDT70125S/L  
STATIC RAM  
WITH BUSY & INTERRUPT  
Features  
Fully asychronous operation from either port  
MASTER IDT70121 easily expands data bus width to 18 bits or  
more using SLAVE IDT70125 chip  
On-chip port arbitration logic (IDT70121 only)  
BUSY output flag on Master; BUSY input on Slave  
INT flag for port-to-port communication  
Battery backup operation—2V data retention  
TTL-compatible, signal 5V (±10%) power supply  
Available in 52-pin PLCC  
High-speed access  
– Commercial: 25/35/55ns (max.)  
– Industrial: 35ns (max.)  
Low-power operation  
– IDT70121/70125S  
Active:675mW(typ.)  
Standby: 5mW (typ.)  
– IDT70121/70125L  
Active:675mW(typ.)  
Standby: 1mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
Green parts available, see ordering information  
FunctionalBlockDiagram  
OER  
OEL  
CE  
R/W  
R
CE  
R/W  
L
R
L
I/O0L- I/O8L  
I/O0R-I/O8R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
R
BUSY  
A
10R  
0R  
A
10L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
0L  
11  
11  
ARBITRATION  
INTERRUPT  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
R
OE  
R
R/W  
L
(2)  
(2)  
L
INT  
INTR  
2654 drw 01  
NOTES:  
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.  
70125 (SLAVE): BUSY is input.  
2. INT is non-tri-stated push-pull output.  
AUGUST 2014  
1
DSC 2654/13  
©2014 Integrated Device Technology, Inc.  

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