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70121L25JG PDF预览

70121L25JG

更新时间: 2024-11-12 00:53:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
16页 170K
描述
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM

70121L25JG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:PLCC
包装说明:QCCJ, LDCC52,.8SQ针数:52
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.26
最长访问时间:25 ns其他特性:INTERRUPT FLAG; AUTOMATIC POWER-DOWN; BATTERY BACKUP
I/O 类型:COMMONJESD-30 代码:S-PQCC-J52
JESD-609代码:e3长度:19.1262 mm
内存密度:18432 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9湿度敏感等级:1
功能数量:1端口数量:2
端子数量:52字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX9输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC52,.8SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
最大待机电流:0.005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.22 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:19.1262 mm
Base Number Matches:1

70121L25JG 数据手册

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HIGH-SPEED  
IDT70121S/L  
IDT70125S/L  
2K x 9 DUAL-PORT  
STATIC RAM  
WITH BUSY & INTERRUPT  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features  
High-speed access  
Fully asychronous operation from either port  
MASTER IDT70121 easily expands data bus width to 18 bits or  
more using SLAVE IDT70125 chip  
On-chip port arbitration logic (IDT70121 only)  
BUSY output flag on Master; BUSY input on Slave  
INT flag for port-to-port communication  
Battery backup operation—2V data retention  
TTL-compatible, signal 5V ( 10%) power supply  
Available in 52-pin PLCC  
– Commercial: 25/35/55ns (max.)  
– Industrial: 35ns (max.)  
Low-power operation  
– IDT70121/70125S  
Active:675mW(typ.)  
Standby: 5mW (typ.)  
– IDT70121/70125L  
Active:675mW(typ.)  
Standby: 1mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available for  
selected speeds  
Green parts available, see ordering information  
Functional Block Diagram  
OER  
OEL  
CER  
CEL  
R/WR  
R/W  
L
I/O0L- I/O8L  
I/O0R-I/O8R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
R
BUSY  
A
10R  
A
10L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
A
0L  
11  
11  
ARBITRATION  
INTERRUPT  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
R
L
R
L
(2)  
(2)  
L
INT  
INTR  
2654 drw 01  
NOTES:  
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.  
70125 (SLAVE): BUSY is input.  
2. INT is non-tri-stated push-pull output.  
OCTOBER 2017  
1
DSC 2654/14  
©2017 Integrated Device Technology, Inc.  

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