Datasheet > 6V49205B_16

6V49205B_16

更新时间： 2024-11-27 01:02:43

品牌	Logo	应用领域
艾迪悌 - IDT		双倍数据速率
页数	文件大小	规格书
16页	275K
描述
Freescale System Clock w/Selectable DDR Frequency

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数据手册

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6V49205B_16 数据手册

Freescale P10XX and P20XX System Clock

w/Selectable DDR Frequency

6V49205B

DATASHEET

General Description

Recommended Application

System Clock for Freescale P10xx and P20xx-based designs

The 6V49205B is a main clock for Freescale P10xx and

P20xx-based systems. It has a selectable System CCB clock

and 2 DDRCLK speeds – 100M or 66.66M. The 6V49205B

also provides LP-HCSL PCIe outputs for low power and

reduced board space.

Features

• Replaces 11 crystals, 2 oscillators and 3 clock generators;

lowers cost, power and area

• Integrated terminations on LP-HCSL PCIe outputs;

Output Features

• 1 - Sys_CCB 3.3V LVCMOS output @ 100M/83.33M/

80M/66.66M

eliminate 24 resistors, saving 41mm of board area

• Industrial temperature range operation; supports

demanding environmental conditions

• 1 - DDRCLK 3.3V LVCMOS output @ 100M or 66.66M

• 1 - 125M 3.3V LVCMOS output

• Advanced 3.3V CMOS process; high-performance,

low-power

• 6 - LP-HCSL PCIe pairs selectable @ 100M or 125M

• 6 - 25MHz 3.3V LVCMOS outputs

• Supports independent spread spectrum on

Sys_CCB/DDRCLK and PCIe outputs

• 2 - 2.048M 3.3V LVCMOS outputs

• 2 - USB 3.3V LVCMOS outputs @12M or 24M

• Available in space-saving 7x7mm 48-pin VFQFPN with

0.5mm pad pitch; reduced board space without the need for

fine-pitch assembly techniques

Key Specifications

• PCIe Gen1-2-3 compliant

• <3p rms phase noise on REF outputs

Block Diagram

Sys_CCB

PLL1

SCLK

(SS)

DDRCLK

SDATA

Control

Logic

^FS0

^FS1

100MHz

^SEL100#_66

PLL4

PCIe_L(5:0)

(SS)

^SELPCIE125#_100

PLL3

(non-

USB_CLK(2:1)

2.048M(1:0)

SS)

Crystal

Oscillator

25MHz

Crystal

PLL2

(non-

SS)

125M

REF(5:0)

GND

Note 1: For DDR Clock: Processor core and I/O supply rails must be ramped with VDD3P3 or earlier. Clock signal will be

clamped LOW and output clock will be 100MHz if this is not followed (see diagram below).

VDD3P3

R40

10K

DDRCLK

R39

10K

6V49205B REVISION R 11/23/16

12 3 4 5 6 7...16

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