Freescale P10XX and P20XX System Clock
with Selectable DDR Frequency
6V49205B
DATASHEET
Description
Typical Applications
System Clock for Freescale P10xx and P20xx-based designs
The 6V49205B is a main clock for Freescale P10xx and
P20xx-based systems. It has a selectable System CCB clock
and 2 DDRCLK speeds – 100M or 66.66M. The 6V49205B
also provides LP-HCSL PCIe outputs for low-power and
reduced board space.
Features
• Replaces 11 crystals, 2 oscillators and 3 clock generators;
lowers cost, power and area
• Integrated terminations on LP-HCSL PCIe outputs;
Output Features
• 1 – Sys_CCB 3.3V LVCMOS output at 100M/83.33M/
80M/66.66M
2
eliminate 24 resistors, saving 41mm of board area
• Industrial temperature range operation; supports
demanding environmental conditions
1
• 1 – DDRCLK 3.3V LVCMOS output at 100M or 66.66M
• 1 – 125M 3.3V LVCMOS output
• Advanced 3.3V CMOS process; high-performance,
low-power
• 6 – LP-HCSL PCIe pairs selectable at 100M or 125M
• 6 – 25MHz 3.3V LVCMOS outputs
• Supports independent spread spectrum on
Sys_CCB/DDRCLK and PCIe outputs
• 2 – 2.048M 3.3V LVCMOS outputs
• 2 – USB 3.3V LVCMOS outputs at 12M or 24M
• Available in space-saving 7 x 7 mm 48-VFQFPN with
0.5mm pad pitch; reduced board space without the need for
fine-pitch assembly techniques
Key Specifications
• PCIe Gen1-2-3 compliant
• < 3p rms phase noise on REF outputs
Block Diagram
Sys_CCB
PLL1
SCLK
(SS)
DDRCLK
SDATA
Control
Logic
^FS0
^FS1
^SEL100#_66
^SELPCIE125#_100
100MHz
PLL4
PCIe_L(5:0)
(SS)
PLL3
(non-
SS)
USB_CLK(2:1)
2.048M(1:0)
X1
25MHz
Crystal
Crystal
Oscillator
PLL2
(non-
SS)
125M
X2
REF(5:0)
GND
Note 1: For DDR Clock: Processor core and I/O supply rails must be ramped with VDD3P3 or earlier. Clock signal will be
clamped LOW and output clock will be 100MHz if this is not followed (see diagram below).
VDD3P3
R40
10K
DDRCLK
R39
10K
6V49205B MAY 5, 2017
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©2017 Integrated Device Technology, Inc.