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5V9888NLGI8

更新时间： 2024-01-08 04:17:13
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
37页 354K
描述
Clock Generator, 500MHz, PQCC28, GREEN, PLASTIC, VFQFPN-28

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中文翻译

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5V9888NLGI8 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：GREEN, PLASTIC, VFQFPN-28
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.83JESD-30 代码：S-PQCC-N28
JESD-609代码：e3长度：7 mm
湿度敏感等级：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：500 MHz封装主体材料：PLASTIC/EPOXY
封装代码：VQCCN封装等效代码：LCC28,.24SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：400 MHz认证状态：Not Qualified
座面最大高度：1 mm子类别：Clock Generators
最大压摆率：12 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

5V9888NLGI8 数据手册

 浏览型号5V9888NLGI8的Datasheet PDF文件第4页浏览型号5V9888NLGI8的Datasheet PDF文件第5页浏览型号5V9888NLGI8的Datasheet PDF文件第6页浏览型号5V9888NLGI8的Datasheet PDF文件第8页浏览型号5V9888NLGI8的Datasheet PDF文件第9页浏览型号5V9888NLGI8的Datasheet PDF文件第10页 
IDT5V9888  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
Feedback-Divider  
N[11:0]andA[3:0]arethebitsusedtoprogramthefeedback-dividerforPLL0(N0andA0)andPLL1(N1andA1). Ifspreadspectrumgenerationisenabled  
foreitherPLL0orPLL1,thenthe SS_OFFSET[5:0]bits(0x61,0x69)wouldbefactoredintotheoverallfeedbackdividervalue. SeetheSPREADSPECTRUM  
GENERATIONsectionformoredetailsonhowtoconfigurePLL0andPLL1whenspreadspectrumisenabled. ThetwoPLLscanalsobeconfiguredforfractional  
divideratios. SeeFRACTIONALDIVIDERformoredetails. ForPLL2,onlytheN[11:0]bits(N2)areusedtoprogramitsfeedbackdividerandthereisnospread  
spectrumgenerationandfractionaldividescapability. The12-bitfeedback-dividerintegervaluesrangefrom1to4095.  
The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2  
PLL0 and PLL1:  
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64  
M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled)  
(Eq. 3)  
(Eq. 4)  
A[3:0] = 0000 = -1  
= 0001 = 1  
= 0010 = 2  
= 0011 = 3  
.
.
.
= 1111 = 15  
Note: A[3:0] < (N[11:0] - 1), must be met when using A.  
PLL2:  
M = N[11:0]  
(Eq. 5)  
TheusercanachieveanevenoroddintegerdivideratioforbothPLL0andPLL1bysettingtheA[3:0]bitsaccordinglyanddisablingthespreadspectrum.  
AfractionaldividecanalsobesetforPLL0andPLL1byusingtheA[3:0]bitsinconjunctionwiththeSS_OFFSET[5:0]bits,whichisdetailedintheFRACTIONAL  
DIVIDERsection. NotethattheVCOhasafrequencyrangeof10MHzto1100MHz. To maintainlowjitter,itisbesttomaximizetheVCOfrequency. Forexample,  
if thereferenceclockis100MHzanda200MHzclockisrequired,toachievethebestjitterperformance,multiplythe100MHzby11togettheVCOrunningat  
thehighestpossiblefrequencyof1100MHzandthendivideitdowntoget200MHz. Orifthereferenceclockis25MHzand20MHzistherequiredclock,multiply  
the25MHzby40togettheVCOrunningat1000MHzandthendivideitdowntoget20MHz. IfNissetto'0x00', theVCOwillslewtotheminimumfrequency.  
Post-Divider  
Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post-  
divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.  
Thereistheoptiontochoosebetweendisablingthepost-divider, utilizingadiv/1, adiv/2, orthe10-bitpost-dividerbyusingthePM[1:0]bits.. Eachbank,  
exceptforOUT1,hasasetofPMbits. Whendisablingthepost-divider,noclockwillappearattheoutputs,butwillremainpoweredon. Thevaluesarelisted  
inthetablebelow.  
P
00  
01  
PM[1:0]  
00  
P Post-Divider  
disabled  
To Outputs  
VCO  
/2  
10  
11  
/2  
01  
div/1  
/ (Q+2)  
10  
div/2  
11  
Q[9:0] + 2 (Eq. 6)  
PM[1:0]  
Post-Divider Diagram  
7
1...45678910...37

中文翻译

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