IDT5V9888
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
PF32
Pin#
NL28
Pin#
Pin Name
CLKIN
I/O
Type
LVTTL
Description
1
4
1
4
I
I
InputClock
XTALIN/REFIN
XTALOUT
LVTTL
CRYSTAL_IN-Referencecrystalinputorexternalreferenceclockinput
5
5
O
I
LVTTL
CRYSTAL_OUT-Referencecrystalfeedback
GIN0/SDAT/TDI
GIN1/SCLK/TCK
GIN2/TMS
19
20
24
27
16
17
21
24
LVTTL(3)
LVTTL(3)
LVTTL(3)
LVTTL(3)
Multi-purposeinputs. CanbeusedforFrequencyControl,SDAT(I2C),orTDI(JTAG).
Multi-Purposeinputs. CanbeusedforFrequencyControl,SCLK(I2C),orTCK(JTAG).
Multi-Purpose inputs. Can be used for Frequency Control or TMS (JTAG).
I
I
WRITE ENABLE
I
Write Enable pin. This pin must be pulled HIGH during normal operation. HIGH =
normal operation, LOW = Enable writing to internal EEPROM.
GIN3/TRST
GIN4/CLK_SEL
SHUTDOWN/OE
25
21
28
22
18
23
I
I
I
LVTTL(3)
LVTTL(3)
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or TRST (JTAG).
Multi-Purposeinputs. CanbeusedforFrequencyControlorinputclockselector.
Enables/disablestheoutputsorpowersdownthechip.TheSPbit(0x1C)controlsthe
polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.)
I2C/JTAG
OUT1
22
6
19
6
I
3-level(2)
LVTTL
I2C (HIGH) or MFC Mode (MID) or JTAG Programming (LOW).
Configurableclockoutput1.Canalsobeusedtobufferthereferenceclock.
Configurableclockoutput2
O
O
O
O
O
OUT2
29
8
25
7
LVTTL
OUT3
LVTTL
Configurableclockoutput3
OUT4
10
11
8
Adjustable(1)
Adjustable(1)
Configurableclockoutput4,Single-EndedorDifferentialwhencombinedwithOUT4
OUT4
9
Configurable complementary clock output 4, Single-Ended or Differential when
combinedwithOUT4
OUT5
15
16
13
14
O
O
Adjustable(1)
Adjustable(1)
Configurableclockoutput5,Single-EndedorDifferentialwhencombinedwithOUT5
OUT5
Configurable complementary clock output 5, Single-Ended or Differential when
combinedwithOUT5
OUT6
13
31
11
27
O
O
LVTTL
LVTTL(3)
Configurableclockoutput6
GOUT0/TDO/LOSS_LOCK
Multi-PurposeOutput.CanbeprogrammedtouseasPLLLOCKsignal,LOSS_LOCK
or TDO in JTAG mode.
GOUT1/LOSS_CLKIN
3
3
O
LVTTL
Multi-Purpose Output. Can be programmed to use as LOSS_CLKIN.
3.3V Power Supply
VDD
7,12,17, 10,15,20
23,26,32
28
GND
2,9,14,
18,30
2,12,26
Ground
NOTES:
1. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.
2. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are internally biased to VDD/2. They are not hot-insertable or over voltage tolerant.
3. The JTAG (TDO, TMS, TCLK, TRST, and TDI) and I2C (SCLK and SDAT) signals share the same pins with GIN signals.
4