54LVTH162373

更新时间： 2024-11-03 21:53:19

品牌	Logo	应用领域
麦斯威 - MAXWELL		锁存器
页数	文件大小	规格书
10页	206K
描述
3.3V 16-Bit Transparent D-Type Latches

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中文翻译

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数据手册

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54LVTH162373 数据手册

54LVTH162373

3.3V 16-Bit Transparent

D-Type Latches

1OE

1Q1

1Q2

GND

1Q3

1Q4

VCC

1Q5

1Q6

GND

1Q7

1Q8

2Q1

2Q2

GND

2Q3

2Q4

1LE

Logic Diagram (PositiveLogic)

1D1

1D2

GND

1D3

1D4

VCC

1D5

1D6

GND

1D7

1D8

2D1

2D2

GND

2D3

2D4

VCC

2D5

2D6

GND

2D7

2D8

2LE

1/24

1OE/2OE

48/25

1LE/2LE

2/13

1Q1/2Q1

47/36

54LVTH162373

1D1/2D1

VCC

2Q5

2Q6

GND

2Q7

2Q8

To Seven Other Channels

Logic Diagram

2OE

FEATURES:

DESCRIPTION:

•

3.3V low voltage advanced BiCMOS technology (LVT) 16-

Maxwell Technologies’ 54LVTH162373 16-bit transparent D-

type latches with 3-state output features a greater than 100

krad (Si) total dose tolerance, depending upon space mission.

The 54LVTH162373 is designed for low voltage (3.3V) V_CC

operation, but with the capability to provide a TTL interface to

a 5V system environment. It is suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and working reg-

isters. The 54LVTH162373 can be used as two 8-bit latches or

one 16-bit latch. When the latch-enable (LE) input is low, the

Q output are latched at the levels set up at the data (D) inputs.

When LE is high, the Q outputs follow the D inputs. A buffered

output-enable (OE) input can be used to place the eight out-

puts in either a normal logic state or a high impedance state.

In the high impedance state, the outputs neither load nor drive

the bus lines significantly. The high impedance state and the

increased drive provide the capability to drive bus lines with-

out the need for interface or pullup components. OE does not

affect internal operations of the latch. Old data can be retained

or new data can be entered while the outputs are in the high

impedance state.

bit transparent D-type latches with 3-state outputs

Total dose hardness:

- > 100 krad (Si), depending upon space mission

Excellent Single Event Effect:

- SEL_TH: No LU > 119 MeV/mg/cm²

Package: 48 pin RAD-PAK® flat package

Operating temperature range:

•

- 55 to 125^°C

•

Distributed V_CCand GND pin configuration minimizes high-

speed switching noise

Supports mixed-mode signal operation

- 5V input and output voltages with 3.3V V_CC

Supports unregulated battery operation down to 2.7V

Supports live insertion

•

Bus-hold data inputs eliminate the need for external pullup

resistors

Maxwell Technologies' patented R^AD-PAK® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-

age. It eliminates the need for box shielding while providing

the required radiation shielding for a lifetime in orbit or space

mission. In a GEO orbit, R^AD-PAK provides greater than 100

krad (Si) radiation dose tolerance. This product is available

with screening up to Class S.

1000596

12.19.01 Rev 1

All data sheets are subject to change without notice

(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

12 3 4 5 6 7...10

中文翻译

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与54LVTH162373相关器件

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54LVTH162373RPFB	MAXWELL	获取价格	3.3V 16-Bit Transparent D-Type Latches
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54LVTH16373RPFE	MAXWELL	获取价格	3.3V ABT16-Bit Transparent D-Type Latches
54LVTH16373RPFI	MAXWELL	获取价格	3.3V ABT16-Bit Transparent D-Type Latches
54LVTH16373RPFS	MAXWELL	获取价格	3.3V ABT16-Bit Transparent D-Type Latches
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