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54LVX3384W-QML PDF预览

54LVX3384W-QML

更新时间: 2024-11-03 22:13:39
品牌 Logo 应用领域
美国国家半导体 - NSC 开关逻辑集成电路驱动
页数 文件大小 规格书
6页 100K
描述
10-Bit Low Power Bus Switch

54LVX3384W-QML 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL24,.4Reach Compliance Code:unknown
风险等级:5.92其他特性:TTL COMPATIBLE BUS SWITCH
系列:LV/LV-A/LVX/HJESD-30 代码:R-GDFP-F24
JESD-609代码:e0长度:15.113 mm
逻辑集成电路类型:BUS DRIVER位数:10
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL24,.4
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):0.25 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:2.54 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED

54LVX3384W-QML 数据手册

 浏览型号54LVX3384W-QML的Datasheet PDF文件第2页浏览型号54LVX3384W-QML的Datasheet PDF文件第3页浏览型号54LVX3384W-QML的Datasheet PDF文件第4页浏览型号54LVX3384W-QML的Datasheet PDF文件第5页浏览型号54LVX3384W-QML的Datasheet PDF文件第6页 
April 1999  
54LVX3384  
10-Bit Low Power Bus Switch  
General Description  
Features  
n 4switch connection between two ports  
n Minimal propagation delay through the switch  
The 54LVX3384 provides 10 bits of high-speed CMOS  
TTL-compatible bus switches. The low on resistance of the  
switch allows inputs to be connected to outputs without add-  
ing propagation delay or generating additional ground  
bounce noise. The device is organized as two 5-bit switches  
with separate bus enable (OE ) signals. When OE is low, the  
switch is on and port A is connected to port B. When OE is  
high, the switch is open and a high-impedance state exists  
between the two ports.  
<
n Ultra low power with 0.1 µA typical ICC  
n Zero ground bounce in flow-through mode  
n Control inputs compatible with TTL levels  
n Available in CDIP and Cerpack Packaging  
n Standard Microcircuit Drawing (SMD) 5962-9950701  
Ordering Code  
Order Number  
54LVX3384J-QML  
54LVX3384W-QML  
Package Number  
J24F  
Package Description  
24-Lead Ceramic Dual-in-line  
24-Lead Cerpack  
W24C  
Logic Diagram  
Connection Diagram  
Pin Assignment for  
CDIP and Cerpack  
DS101061-1  
Pin Descriptions  
Pin Names  
OEA, OEB  
A0–A9  
Description  
Bus Switch Enable  
Bus A  
DS101061-2  
Truth Table  
B0–B9  
Bus B  
OEA OEB  
B0–B4  
B5–B9  
A5–A9  
Function  
Connect  
Connect  
L
L
L
A0–A4  
A0–A4  
H
HIGH-Z  
State  
H
H
L
HIGH-Z  
State  
A5–A9  
Connect  
H
HIGH-Z  
State  
HIGH-Z  
State  
Disconnect  
© 1999 National Semiconductor Corporation  
DS101061  
www.national.com  

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