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54LVTH162373RPFB PDF预览

54LVTH162373RPFB

更新时间： 2024-11-26 21:53:19
品牌 Logo 应用领域
麦斯威 - MAXWELL 锁存器
页数 文件大小 规格书
10页 206K
描述
3.3V 16-Bit Transparent D-Type Latches

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中文翻译

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54LVTH162373RPFB 技术参数

生命周期：Contact Manufacturer零件包装代码：DFP
包装说明：DFP,针数：48
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.25
系列：LVTJESD-30 代码：R-XDFP-F48
长度：15.748 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：UNSPECIFIED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：6.5 ns认证状态：Not Qualified
座面最大高度：4.4704 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：FLAT
端子节距：0.635 mm端子位置：DUAL
总剂量：100k Rad(Si) V宽度：9.652 mm
Base Number Matches：1

54LVTH162373RPFB 数据手册

 浏览型号54LVTH162373RPFB的Datasheet PDF文件第2页浏览型号54LVTH162373RPFB的Datasheet PDF文件第3页浏览型号54LVTH162373RPFB的Datasheet PDF文件第4页浏览型号54LVTH162373RPFB的Datasheet PDF文件第5页浏览型号54LVTH162373RPFB的Datasheet PDF文件第6页浏览型号54LVTH162373RPFB的Datasheet PDF文件第7页 
54LVTH162373  
3.3V 16-Bit Transparent  
D-Type Latches  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
VCC  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1
48  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
VCC  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
VCC  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
1/24  
1OE/2OE  
48/25  
1LE/2LE  
C1  
1D  
2/13  
1Q1/2Q1  
47/36  
54LVTH162373  
1D1/2D1  
VCC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
To Seven Other Channels  
Logic Diagram  
2OE  
24  
25  
FEATURES:  
DESCRIPTION:  
•
•
•
3.3V low voltage advanced BiCMOS technology (LVT) 16-  
Maxwell Technologies’ 54LVTH162373 16-bit transparent D-  
type latches with 3-state output features a greater than 100  
krad (Si) total dose tolerance, depending upon space mission.  
The 54LVTH162373 is designed for low voltage (3.3V) VCC  
operation, but with the capability to provide a TTL interface to  
a 5V system environment. It is suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and working reg-  
isters. The 54LVTH162373 can be used as two 8-bit latches or  
one 16-bit latch. When the latch-enable (LE) input is low, the  
Q output are latched at the levels set up at the data (D) inputs.  
When LE is high, the Q outputs follow the D inputs. A buffered  
output-enable (OE) input can be used to place the eight out-  
puts in either a normal logic state or a high impedance state.  
In the high impedance state, the outputs neither load nor drive  
the bus lines significantly. The high impedance state and the  
increased drive provide the capability to drive bus lines with-  
out the need for interface or pullup components. OE does not  
affect internal operations of the latch. Old data can be retained  
or new data can be entered while the outputs are in the high  
impedance state.  
bit transparent D-type latches with 3-state outputs  
Total dose hardness:  
- > 100 krad (Si), depending upon space mission  
Excellent Single Event Effect:  
- SELTH: No LU > 119 MeV/mg/cm2  
Package: 48 pin RAD-PAK® flat package  
Operating temperature range:  
•
•
- 55 to 125°C  
•
•
Distributed VCC and GND pin configuration minimizes high-  
speed switching noise  
Supports mixed-mode signal operation  
- 5V input and output voltages with 3.3V VCC  
Supports unregulated battery operation down to 2.7V  
Supports live insertion  
•
•
•
Bus-hold data inputs eliminate the need for external pullup  
resistors  
Maxwell Technologies' patented RAD-PAK® packaging technol-  
ogy incorporates radiation shielding in the microcircuit pack-  
age. It eliminates the need for box shielding while providing  
the required radiation shielding for a lifetime in orbit or space  
mission. In a GEO orbit, RAD-PAK provides greater than 100  
krad (Si) radiation dose tolerance. This product is available  
with screening up to Class S.  
1000596  
12.19.01 Rev 1  
1
All data sheets are subject to change without notice  
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com  
©2001 Maxwell Technologies  
All rights reserved.  
1234567...10

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