Datasheet > 54LVX4245_993

54LVX4245_993

更新时间： 2024-02-02 19:28:54

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
8页	120K
描述
8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs

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54LVX4245_993 数据手册

March 1999

54LVX4245

8-Bit Dual Supply Translating Transceiver with

TRI-STATE^®Outputs

General Description

Features

n Bidirectional interface between 5V and 3V buses

n Control inputs compatible with TTL level

The LVX4245 is a dual-supply, 8-bit translating transceiver

that is designed to interface between a 5V bus and a 3V bus

in a mixed 3V/5V supply environment. The Transmit/Receive

(T/R) input determines the direction of data flow. Transmit

(active-HIGH) enables data from A ports to B ports; Receive

(active-LOW) enables data from B ports to A ports. The

Output Enable input, when HIGH, disables both A and B

ports by placing them in a TRI-STATE condition. The A port

interfaces with the 5V bus; the B port interfaces with the 3V

bus.

n 5V data flow at A port and 3V data flow at B port

n Outputs source/sink 24 mA

n Available in Ceramic DIP and Flatpack packages

n Implements patented EMI reduction circuitry

n Functionally compatible with the 54 series 245

n Standard Microcircuit Drawing (SMD) 5962-9860601

The LVX4245 is suitable for mixed voltage applications such

as systems using 3.3V memories which must interface with

existing buses or other components operating at 5.0V.

Ordering Code

Order Number

54LVX4245J-QML

54LVX4245W-QML

Package Number

J24F

Package Description

24-Lead Ceramic Dual-in-line

24-Lead Cerpack

W24C

Logic Symbol

Connection Diagram

Pin Assignment for

CDIP and Cerpack

DS101021-1

Pin Descriptions

Pin Names

Description

Output Enable Input

Transmit/Receive Input

T/R

A₀–A₇

B₀–B₇

Side A Inputs or TRI-STATE Outputs

Side B Inputs or TRI-STATE Outputs

DS101021-2

TRI-STATE^®is a registered trademark of National Semiconductor

DS101021

www.national.com

12 3 4 5 6 7 8

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