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54LVX4245J-QML PDF预览

54LVX4245J-QML

更新时间： 2024-01-15 21:54:55
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器逻辑集成电路输入元件
页数 文件大小 规格书
8页 122K
描述
8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs

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中文翻译

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54LVX4245J-QML 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：DIP, DIP24,.3Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.92Is Samacsys：N
其他特性：5V SUPPLY FOR PORT A; 3.3V SUPPLY FOR PORT B; 3.3V OR 5V TTL COMPATIBLE CONTROL INPUTS控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：LV/LV-A/LVX/H
JESD-30 代码：R-GDIP-T24JESD-609代码：e0
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：8.5 ns
传播延迟（tpd）：9 ns认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：4.572 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：3V & 5V宽度：15.24 mm
Base Number Matches：1

54LVX4245J-QML 数据手册

 浏览型号54LVX4245J-QML的Datasheet PDF文件第2页浏览型号54LVX4245J-QML的Datasheet PDF文件第3页浏览型号54LVX4245J-QML的Datasheet PDF文件第4页浏览型号54LVX4245J-QML的Datasheet PDF文件第5页浏览型号54LVX4245J-QML的Datasheet PDF文件第6页浏览型号54LVX4245J-QML的Datasheet PDF文件第7页 
January 1999  
54LVX4245  
8-Bit Dual Supply Translating Transceiver with  
TRI-STATE® Outputs  
General Description  
Features  
n Bidirectional interface between 5V and 3V buses  
n Control inputs compatible with TTL level  
The LVX4245 is a dual-supply, 8-bit translating transceiver  
that is designed to interface between a 5V bus and a 3V bus  
in a mixed 3V/5V supply environment. The Transmit/Receive  
(T/R) input determines the direction of data flow. Transmit  
(active-HIGH) enables data from A ports to B ports; Receive  
(active-LOW) enables data from B ports to A ports. The Out-  
put Enable input, when HIGH, disables both A and B ports by  
placing them in a TRI-STATE condition. The A port interfaces  
with the 5V bus; the B port interfaces with the 3V bus.  
n 5V data flow at A port and 3V data flow at B port  
n Outputs source/sink 24 mA  
n Available in Ceramic DIP and Flatpack packages  
n Implements patented EMI reduction circuitry  
n Functionally compatible with the 54 series 245  
n Standard Microcircuit Drawing (SMD) 5962-9860601  
The LVX4245 is suitable for mixed voltage applications such  
as systems using 3.3V memories which must interface with  
existing buses or other components operating at 5.0V.  
Ordering Code  
Order Number  
54LVX4245J-QML  
54LVX4245W-QML  
Package Number  
J24F  
Package Description  
24-Lead Ceramic Dual-in-line  
24-Lead Cerpack  
W24C  
Logic Symbol  
Connection Diagram  
Pin Assignment for  
CDIP and Cerpack  
DS101021-1  
Pin Descriptions  
Pin Names  
Description  
OE  
Output Enable Input  
Transmit/Receive Input  
T/R  
A0–A7  
B0–B7  
Side A Inputs or TRI-STATE Outputs  
Side B Inputs or TRI-STATE Outputs  
DS101021-2  
TRI-STATE® is a registered trademark of National Semiconductor  
© 1999 National Semiconductor Corporation  
DS101021  
www.national.com  
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