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54LVXC4245W-QML PDF预览

54LVXC4245W-QML

更新时间： 2024-11-26 22:13:39
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
9页 119K
描述
8-Bit Dual Supply Configurable Voltage Interface Transceiver with TRI-STATE Outputs

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54LVXC4245W-QML 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DFP, FL24,.4Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.91其他特性：5V SUPPLY FOR PORT A; 2.7V TO 5.5V SUPPLY FOR PORT B; 3.3V OR 5V TTL COMPATIBLE CONTROL INPUTS
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：LV/LV-A/LVX/HJESD-30 代码：R-GDFP-F24
JESD-609代码：e0长度：15.113 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL24,.4封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5,5 VProp。Delay @ Nom-Sup：9.5 ns
传播延迟（tpd）：9.5 ns认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：2.54 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：3/5V & 5VBase Number Matches：1

54LVXC4245W-QML 数据手册

 浏览型号54LVXC4245W-QML的Datasheet PDF文件第2页浏览型号54LVXC4245W-QML的Datasheet PDF文件第3页浏览型号54LVXC4245W-QML的Datasheet PDF文件第4页浏览型号54LVXC4245W-QML的Datasheet PDF文件第5页浏览型号54LVXC4245W-QML的Datasheet PDF文件第6页浏览型号54LVXC4245W-QML的Datasheet PDF文件第7页 
March 1999  
54LVXC4245  
8-Bit Dual Supply Configurable Voltage Interface  
Transceiver with TRI-STATE® Outputs  
General Description  
Features  
n Bidirectional interface between 5V and 3V-to-5V buses  
n Control inputs compatible with TTL level  
n Outputs source/sink up to 24 mA  
The LVXC4245 is a 24-pin dual-supply, 8-bit configurable  
voltage interface transceiver suited for real time configurable  
I/O applications. The VCCA pin accepts a 5V supply level.  
The “A” port is a dedicated 5V port. The VCCB pin accepts a  
3V-to-5V supply level. The “B” port is configured to track the  
n Available in Cerpack and CDIP packages  
n Implements patented EMI reduction circuitry  
n Flexible VCCB operating range  
n Allows B port and VCCB to float simultaneously when OE  
is HIGH  
V
CCB supply level respectively. A 5V level on the VCC pin will  
configure the I/O pins at a 5V level and a 3V VCC will config-  
ure the I/O pins at a 3V level. This device will allow the VCCB  
voltage source pin and I/O pins on the “B” port to float when  
OE is HIGH. This feature is necessary to buffer data to and  
from a socket that permits live insertion and removal during  
normal operation.  
n Functionally compatible with the 54 series 245  
n Standard Microcircuit Drawing (SMD) 5962-9862001  
Ordering Code  
Order Number  
54LVXC4245W-QML  
54LVXC4245J-QML  
Package Number  
W24C  
Package Description  
24-Lead Ceramic Flatpack  
24-Lead Ceramic Dual-in-line  
J24F  
Logic Symbol  
Connection Diagram  
Pin Assignment  
for Cerpack and CDIP  
DS101033-1  
Pin Descriptions  
Pin Names  
Description  
Output Enable Input  
Transmit/Receive Input  
OE  
T/R  
A0–A7  
B0–B7  
Side A Inputs or TRI-STATE Outputs  
Side B Inputs or TRI-STATE Outputs  
DS101033-2  
TRI-STATE® is a registered trademark of National Semiconductor Corporation  
© 1999 National Semiconductor Corporation  
DS101033  
www.national.com  
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