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54LVXC4245J-QML PDF预览

54LVXC4245J-QML

更新时间: 2024-01-07 21:18:18
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器逻辑集成电路输入元件
页数 文件大小 规格书
9页 119K
描述
8-Bit Dual Supply Configurable Voltage Interface Transceiver with TRI-STATE Outputs

54LVXC4245J-QML 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.3Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.91其他特性:5V SUPPLY FOR PORT A; 2.7V TO 5.5V SUPPLY FOR PORT B; 3.3V OR 5V TTL COMPATIBLE CONTROL INPUTS
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LV/LV-A/LVX/HJESD-30 代码:R-GDIP-T24
JESD-609代码:e0逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/5,5 V
Prop。Delay @ Nom-Sup:9.5 ns传播延迟(tpd):9.5 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:4.572 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:3/5V & 5V
宽度:15.24 mmBase Number Matches:1

54LVXC4245J-QML 数据手册

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March 1999  
54LVXC4245  
8-Bit Dual Supply Configurable Voltage Interface  
Transceiver with TRI-STATE® Outputs  
General Description  
Features  
n Bidirectional interface between 5V and 3V-to-5V buses  
n Control inputs compatible with TTL level  
n Outputs source/sink up to 24 mA  
The LVXC4245 is a 24-pin dual-supply, 8-bit configurable  
voltage interface transceiver suited for real time configurable  
I/O applications. The VCCA pin accepts a 5V supply level.  
The “A” port is a dedicated 5V port. The VCCB pin accepts a  
3V-to-5V supply level. The “B” port is configured to track the  
n Available in Cerpack and CDIP packages  
n Implements patented EMI reduction circuitry  
n Flexible VCCB operating range  
n Allows B port and VCCB to float simultaneously when OE  
is HIGH  
V
CCB supply level respectively. A 5V level on the VCC pin will  
configure the I/O pins at a 5V level and a 3V VCC will config-  
ure the I/O pins at a 3V level. This device will allow the VCCB  
voltage source pin and I/O pins on the “B” port to float when  
OE is HIGH. This feature is necessary to buffer data to and  
from a socket that permits live insertion and removal during  
normal operation.  
n Functionally compatible with the 54 series 245  
n Standard Microcircuit Drawing (SMD) 5962-9862001  
Ordering Code  
Order Number  
54LVXC4245W-QML  
54LVXC4245J-QML  
Package Number  
W24C  
Package Description  
24-Lead Ceramic Flatpack  
24-Lead Ceramic Dual-in-line  
J24F  
Logic Symbol  
Connection Diagram  
Pin Assignment  
for Cerpack and CDIP  
DS101033-1  
Pin Descriptions  
Pin Names  
Description  
Output Enable Input  
Transmit/Receive Input  
OE  
T/R  
A0–A7  
B0–B7  
Side A Inputs or TRI-STATE Outputs  
Side B Inputs or TRI-STATE Outputs  
DS101033-2  
TRI-STATE® is a registered trademark of National Semiconductor Corporation  
© 1999 National Semiconductor Corporation  
DS101033  
www.national.com  

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