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2SK3585G

更新时间： 2024-01-04 06:23:28
品牌 Logo 应用领域
松下 - PANASONIC 开关光电二极管晶体管
页数 文件大小 规格书
3页 263K
描述
Small Signal Field-Effect Transistor, 0.00046A I(D), 1-Element, N-Channel, Silicon, Junction FET, ROHS COMPLIANT, SSSMINI3-F2, 3 PIN

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2SK3585G 技术参数

是否Rohs认证：符合生命周期：Obsolete
包装说明：SMALL OUTLINE, R-PDSO-F3针数：3
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8541.21.00.95风险等级：5.84
Is Samacsys：N其他特性：LOW NOISE
配置：SINGLE WITH BUILT-IN DIODE最大漏极电流 (ID)：0.00046 A
FET 技术：JUNCTIONJESD-30 代码：R-PDSO-F3
元件数量：1端子数量：3
工作模式：DEPLETION MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子形式：FLAT端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

2SK3585G 数据手册

 浏览型号2SK3585G的Datasheet PDF文件第2页浏览型号2SK3585G的Datasheet PDF文件第3页 
This product complies with the RoHS Directive (EU 2002/95/EC).  
Silicon Junction FETs (Small Signal)  
2SK3585G  
Silicon N-channel junction FET  
For impedance conversion in low frequency  
For electret capacitor microphone  
Package  
Features  
ꢀCode  
High mutual conductance gm  
Low noise voltage NV  
SSSMini3-F2  
ꢀPin Name  
1: rain  
Absolute Maximum Ratings Ta = 25°C  
ce  
Parameter  
Symbol  
VDSO  
VDGO  
IDSO  
Rating  
Unit  
V
Drain-source voltage (Gate open)  
Drain-gate voltage (Souece open)  
Drain-source current (Gate open)  
Drain-gate current (Souece open)  
Gate-source cut-off current (Drain open)  
Power dissipation  
20  
2
V
Marking Symbol: 5K  
mA  
mA  
mA  
mW  
°C  
IDO  
IGSO  
2
PD  
100  
Operating ambient temperature  
Storage temperature  
Tor  
–20 to +0  
–55 to +125  
T
stg  
°C  
Electrical Characteristics Ta = 25°C±
Paam
Sym
ID  
Conditions  
Min  
100  
107  
660  
Typ  
Max  
460  
470  
Unit  
mA  
mA  
mS  
1
Drain currnt
VDS = 2.0 V, Rd = 2.2 kW ± 1%  
VDS = 2.0 V, Rd = 2.2 kW ± 1%, VGS = 0  
VD = 2.0 V, VGS = 0, f = 1 kHz  
Din-source curret  
Mutul conduance  
IDSS  
gm  
1600  
VD = 2.0 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, A-curve  
Noise voltage  
Voltage gain  
NV  
GV1  
GV2  
GV3  
4
mV  
VD = 2.0 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
–7.5  
–4.0  
–8.0  
–4.7  
–1.5  
–5.0  
VD = 12 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
dB  
VD = 1.5 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV, f = 1 kHz  
VD = 2.0 V, Rd = 2.2 kW ± 1%  
CO = 5 pF, eG = 10 mV  
f = 1 kHz to 70 Hz  
2
DGV . f*  
0
1.7  
0
0
8
4.0  
1.7  
15  
GV2 – GV1  
GV1 – GV3  
Rg  
Voltage gain difference  
Gate resistance  
dB  
VGS = 0.05 V  
GW  
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.  
2. A protection diode is built-in between gate and source of transistor. However if forward current flows between gate and source transistor  
might be damaged. So please be careful not insert reverse.  
3. *1: ID is assured for IDSS  
.
2: D|GV . f | is assured for AQL 0.065. (The measurement method is used by source-grounded circuit.)  
*
Publication date: October 2008  
SJF00109AED  
1
123

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