Datasheet > ZSSC3018BA2D

ZSSC3018BA2D

更新时间： 2024-01-24 15:55:02

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
50页	1237K
描述
Versatile, High Resolution 18-Bit Sensor Signal Conditioner

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ZSSC3018BA2D 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	WAFER
针数：	0	Reach Compliance Code：	compliant
风险等级：	5.57	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-609代码：	e3	湿度敏感等级：	1
峰值回流温度（摄氏度）：	NOT SPECIFIED	端子面层：	Tin (Sn)
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

ZSSC3018BA2D 数据手册

ZSSC3018 Datasheet

1. IC Characteristics

1.1 Absolute Maximum Ratings

Note: The absolute maximum ratings are stress ratings only. The ZSSC3018 might not function or be operable above the recommended

operating conditions. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to

stresses above the recommended operating conditions might affect device reliability. IDT does not recommend designing to the “Absolute

Maximum Ratings.”

Table 1.1 Absolute Maximum Ratings

PARAMETER

SYMBOL

Vss

Min

TYP

MAX

UNITS

Voltage Reference

–

Analog Supply Voltage

V_DD

-0.4

-0.5

-100

3.63

V_DD+0.5

100

Voltage at all Analog and Digital IO Pins

V_{A_IO}, V_{D_IO}

I_IN

Input Current into any Pin except RES, TEST1, TEST2, TEST3, TEST4,

TEST5, and SS ^{[a], [b]}

Electrostatic Discharge Tolerance – Human Body Model (HBM1) ^[c]

V_HBM1

T_STOR

4000

-50

–

Storage Temperature

130

°C

[a] Latch-up current limit for RES, TEST1, TEST2, TEST3, TEST4, TEST5, and SS: ±70mA.

[b] Latch-up resistance; reference for pin is 0V.

[c] HBM1: C = 100pF charged to V_HBM1with resistor R = 1.5k in series based on MIL 883, Method 3015.7. ESD protection

referring to the Human Body Model is tested with devices in ceramic dual in-line packages (CDIP) during product qualification.

1.2 Operating Conditions

Note: The reference for all voltages is Vss.

Table 1.2 Operating Conditions

PARAMETER

SYMBOL

V_DD

MIN

1.68

–

TYP

–

MAX

3.6

UNIT

Supply Voltage

VDD Rise Time

t_VDD

–

200

1.8

μs

–

Bridge Current ^[a]

I_VDDB

–

16.5

125

Operation Temperature Range

T_AMB

C_L

-40

0.01

–

°C

External (Parasitic) Capacitance between VDDB and VSS

–

[a] Power supply rejection is reduced if a current in the range of 16.5mA > I_VDDB> 1.8mA is drawn out of VDDB.

A dynamic power-on-reset circuit is implemented in order to achieve the minimum current consumption in Sleep Mode. The VDD low level,

the subsequent rise time, and the VDD rising slope must meet the requirements in Table 1.3 to guarantee an overall IC reset: lower VDD low

levels allow slower rising of the subsequent on-ramp of VDD. Other combinations might also be possible. For example, the reset trigger can

be influenced by increasing the power-down time and lowering the VDD rising slope requirement. Alternatively, the RES pin can be connected

and used to control safe resetting of the IC. RES is low-active – a VDD-VSS-VDD transition at the RES pin leads to a complete ZSSC3018

reset.

January 10, 2017

1...3 4 567 8 9...50

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