Datasheet > Z8S18008VSC

Z8S18008VSC

更新时间： 2024-11-04 22:07:55

品牌	Logo	应用领域
ZILOG		微处理器
页数	文件大小	规格书
70页	386K
描述
ENHANCED Z180 MICROPROCESSOR

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Z8S18008VSC 数据手册

PRELIMINARY PRODUCT SPECIFICATION

Z80180/Z8S180/

Z8L180 SL1919

ENHANCED Z180 MICROPROCESSOR

FEATURES

■ Code Compatible with Zilog Z80 CPU

■ Two 16-Bit Counter/Timers

■ Extended Instructions

■ Two Enhanced UARTs (up to 512 Kbps)

■ Clock Speeds: 6, 8, 10, 20, 33 MHz

■ Operating Range: 5V (3.3V@ 20 MHz)

■ Two Chain-Linked DMA Channels

■ Low Power-Down Modes

■ On-Chip Interrupt Controllers

■ Three On-Chip Wait-State Generators

■ On-Chip Oscillator/Generator

■ Expanded MMU Addressing (up to 1 MB)

■ Clocked Serial I/O Port

■ Operating Temperature Range: 0 C to +70 C

■ -40 C to +85 C Extended Temperature Range

■ Three Packaging Styles

–

68-Pin PLCC

64-Pin DIP

80-Pin QFP

GENERAL DESCRIPTION

™

The enhanced Z80180/Z8S180/Z8L180 significantly im-

Not only does the Z80180/Z8S180/Z8L180 consume less

power during normal operations than the previous model,

it has also been designed with three modes intended to fur-

proves on the previous Z80180 models while still providing

full backward compatibility with existing Zilog Z80 devices.

The Z80180/Z8S180/Z8L180 now offers faster execution

speeds, power saving modes, and EMI noise reduction.

ther reduce the power consumption. Zilog reduced I pow-

er consumption during STANDBY Mode to a minimum of

10 µA by stopping the external oscillators and internal

clock. The SLEEP mode reduces power by placing the

CPU into a “stopped” state, thereby consuming less cur-

rent while the on-chip I/O device is still operating. The

SYSTEM STOP mode places both the CPU and the on-

chip peripherals into a “stopped” mode, thereby reducing

power consumption even further.

This enhanced Z180 design also incorporates additional

feature enhancements to the ASCIs, DMAs, and I

STANDBY Mode power consumption. With the addition of

“ESCC-like” Baud Rate Generators (BRGs), the two ASCIs

now have the flexibility and capability to transfer data asyn-

chronously at rates of up to 512 Kbps. In addition, the ASCI

receiver has added a 4-byte First In First Out (FIFO) which

can be used to buffer incoming data to reduce the inci-

dence of overrun errors. The DMAs have been modified to

allow for a “chain-linking” of the two DMA channels when

set to take their DMA requests from the same peripherals

device. This feature allows for non-stop DMA operation be-

tween the two DMA channels, reducing the amount of CPU

intervention (Figure 1).

A new clock doubler feature has been implemented in the

Z80180/Z8S180/Z8L180 device that allows the program-

mer to double the internal clock from that of the external

clock. This provides a systems cost savings by allowing

the use of lower cost, lower frequency crystals instead of

the higher cost, and higher speed oscillators.

The Enhanced Z180 is housed in 80-pin QFP, 68-pin

PLCC, and 64-pin DIP packages.

DS971800401

P R E L I M I N A R Y

1-1

12 3 4 5 6 7...70

中文翻译

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与Z8S18008VSC相关器件

型号	品牌	获取价格	描述	数据表
Z8S18010FEC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18010FEG	IXYS	获取价格	IC 8-BIT, 10 MHz, MICROPROCESSOR, PQFP80, QFP-80, Microprocessor
Z8S18010FSC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18010FSG	ZILOG	获取价格	IC 8-BIT, 10 MHz, MICROPROCESSOR, PQFP80, QFP-80, Microprocessor
Z8S18010PEC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18010PEG	IXYS	获取价格	IC 8-BIT, 10 MHz, MICROPROCESSOR, PDIP64, PLASTIC, DIP-64, Microprocessor
Z8S18010PSC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18010VEC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18010VSC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18010VSG	ZILOG	获取价格	IC 8-BIT, 10 MHz, MICROPROCESSOR, PQCC68, PLASTIC, LCC-68, Microprocessor

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