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XRK32308ID-3 PDF预览

XRK32308ID-3

更新时间: 2024-09-16 03:11:47
品牌 Logo 应用领域
艾科嘉 - EXAR 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
16页 374K
描述
3.3V ZERO DELAY BUFFER

XRK32308ID-3 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:LSOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N系列:32308
输入调节:MUXJESD-30 代码:R-PDSO-G16
长度:9.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.008 A功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LSOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.4 ns
座面最大高度:1.5 mm子类别:Clock Driver
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mm最小 fmax:120 MHz
Base Number Matches:1

XRK32308ID-3 数据手册

 浏览型号XRK32308ID-3的Datasheet PDF文件第2页浏览型号XRK32308ID-3的Datasheet PDF文件第3页浏览型号XRK32308ID-3的Datasheet PDF文件第4页浏览型号XRK32308ID-3的Datasheet PDF文件第5页浏览型号XRK32308ID-3的Datasheet PDF文件第6页浏览型号XRK32308ID-3的Datasheet PDF文件第7页 
PRELIMINARY  
XRK32308  
3.3V ZERO DELAY BUFFER  
FEBRUARY 2007  
REV.P1.0.3  
The XRK32308–1H is the high-drive version of the –  
1. Rise and fall times on this device are faster.  
GENERAL DESCRIPTION  
FUNCTIONAL DESCRIPTION  
The XRK32308–2 allows the user to obtain 1X, and  
XRK32308 is a 3.3V Zero Delay Buffer designed to 2X or X/2 depending on which Bank sources the FB  
distribute high-speed clocks in PC, workstation, signal.  
datacom, telecom, and other high-performance  
applications.  
The XRK32308–3 allows the user to obtain 4X and  
2X frequencies or 1X and 2X.  
The part has an on-chip PLL which locks to an input  
The XRK32308–4 enables the user to obtain 2X  
clock presented on the REF pin. The PLL feedback is  
clocks on all outputs.  
required to be driven into the FB pin, and can be  
The XRK32308–5H is a high-drive version with REF/  
2 on both banks.  
obtained from one of the outputs. The input-to-output  
skew is guaranteed to be less than 350 ps, and  
output-to-output skew is guaranteed to be less than  
200 ps.  
FEATURES  
Zero input-output propagation delay, adjustable by  
XRK32308 has two banks of four outputs each.  
These can be controlled by the Select inputs as  
shown in Table 2, “Select Input Decoding,” on page 2.  
If all output clocks are not required, Bank B can be  
three-stated. The select inputs also allow the input  
clock to be directly applied to the output for chip and  
system testing purposes.  
capacitive load on FB input  
Multiple configurations, see “Available XRK32308  
Configurations” table  
Multiple low-skew outputs  
Two banks of four outputs, three-stateable by two  
select inputs  
Multiple XRK32308 devices can accept the same  
input clock and distribute it in a system. In this case,  
the skew between the outputs of two devices is  
guaranteed to be less than 700 ps.  
10-MHz to 120-MHz operating range  
75ps typical cycle-to-cycle jitter (15pF, 66MHz)  
Space-saving 16-pin 150-mil SOIC package, 16-pin  
TSSOP or 16-pin QFN  
XRK32308 devices are available in five different  
configurations, as shown in Table 3, “Available  
XRK32308 Configurations,” on page 3.  
3.3V operation  
Industrial and commercial temperature available  
The XRK32308–1 is the base part, where the output  
frequencies equal the reference if there is no counter  
in the feedback path.  
FIGURE 1. BLOCK DIAGRAM AND PIN CONFIGURATION OF THE XRK32308  
QA0 REF FB QA3  
/2  
FB  
REF  
QA0  
QA1  
VDD  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
FB  
PLL  
MUX  
REF  
QA0  
QA1  
QA2  
QA3  
/2  
QA3  
QA2  
VDD  
GND  
QB3  
QB2  
S1  
16  
15  
14  
13  
QA1  
VDD  
GND  
QB0  
1
2
3
4
12  
11  
10  
QA2  
VDD  
GND  
QB3  
Extra Divider (-3, -4)  
Extra Divider (-5H)  
GND  
QB0  
QB1  
S2  
S2  
Select Input  
Decoding  
9
S1  
/2  
5
6
7
8
QB0  
QB1  
QB2  
QB3  
QB1 S2 S1 QB2  
Extra Divider (-2, -3)  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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