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XR16L788
HIGH PERFORMANCE OCTAL UART
SEPTEMBER 2001
REV. 1.1.4
NEW FEATURES:
GENERAL DESCRIPTION
• 5V and 3.3V with 5V Tolerant Inputs Operation
• Single Interrupt Output for all 8 UARTs
• Global Interrupt Source for all 8 UARTs
• 5G “Flat” UART Registers for Configurations
• Simultaneous UART Channels Initialization
The XR16L7881 (788), formerly XR16L758, is a 5V
and 3.3V with 5V tolerant inputs octal Universal Asyn-
chronous Receiver and Transmitter (UART). The
highly integrated device is designed for high band-
width requirement in communication systems. A new
feature increases device driver efficiency includes a
global interrupt pin with global interrupt source regis-
ters that provide complete and detailed interrupt sta-
tus information for all 8 channels that will speed up in-
terrupt parsing. Other new facilities include simulta-
neous UART registers initialization, individual UART
channel soft-reset, DTR/DSR hardware flow control,
software flow control (Xoff/Xon) detection indicators,
RS-485 half-duplex direction control with programma-
ble turn-around delay, Intel or Motorola bus interface
and sleep mode now has a wake-up indicator.
• Auto RS485 Half-duplex Control with Program-
mable Turn-around Delay
• A General Purpose 16-bit Timer/Counter
• Sleep Mode with Wake-up Indication
• Highly Integrated Device for Space Saving
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First eight registers are 16C550 compatible
64-byte Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Programmable TX and RX FIFO Trigger Levels
Automatic RTS/CTS or DTR/DSR Flow Control
Selectable Hardware Flow Control Hysteresis
NOTE: Covered by US patents #5,649,122 and #5,949,787
APPLICATIONS
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Remote Access Servers
Automatic Xon/Xoff Software Flow Control with Sta-
tus Indicator
Ethernet Network to Serial Ports
Network Management
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Infrared (IrDA 1.0) Data Encoder/Decoder
Programmable Data Rate with Prescaler
Up to 6.25 Mbps Serial Data Rate at 5V
100-pin QFP Package (14x20x3 mm)
Factory Automation and Process Control
Point-of-Sale Systems
Multi-port RS-232/RS-422/RS-485 Cards
FIGURE 1. BLOCK DIAGRAM
UART Channel 0
64 Byte TX FIFO
TX0, RX0, DTR0#,
UART
Regs
IR
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
TX & RX
ENDEC
BRG
64 Byte RX FIFO
RST#
A7:A0
UART Channel 1
D7:D0
UART Channel 2
UART Channel 3
UART Channel 4
UART Channel 5
Data Bus
Interface
Device
Configuration
Registers
IOR#
IOW #
CS#
INT#
16/68#
UART Channel 6
TX7, RX7, DTR7#,
DSR7#, RTS7#,
UART Channel 7
16-bit
Tim er/Counter
CTS7#, CD7#, RI7#
XTAL1
XTAL2
TM RCK
Crystal Osc/Buffer
EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com • uarttechsupport@exar.com