Datasheet > XCV1000-4BGG560I

XCV1000-4BGG560I

更新时间： 2024-01-31 00:20:00

品牌	Logo	应用领域
赛灵思 - XILINX		时钟栅可编程逻辑
页数	文件大小	规格书
76页	530K
描述
Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 250MHz, CMOS, PBGA560, BGA-560

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XCV1000-4BGG560I 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	560
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.8	最大时钟频率：	250 MHz
CLB-Max的组合延迟：	0.8 ns	JESD-30 代码：	S-PBGA-B560
JESD-609代码：	e1	长度：	42.5 mm
湿度敏感等级：	3	可配置逻辑块数量：	6144
等效关口数量：	1124022	端子数量：	560
组织：	6144 CLBS, 1124022 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	260
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压：	2.625 V
最小供电电压：	2.375 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
端子面层：	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	42.5 mm
Base Number Matches：	1

XCV1000-4BGG560I 数据手册

Virtex™ 2.5 V

Field Programmable Gate Arrays

DS003-2 (v2.8.1) December 9, 2002

Product Specification

The output buffer and all of the IOB control signals have

independent polarity controls.

Architectural Description

Virtex Array

The Virtex user-programmable gate array, shown in

Figure 1, comprises two major configurable elements: con-

figurable logic blocks (CLBs) and input/output blocks

(IOBs).

DLL

IOBs

DLL

VersaRing

•

CLBs provide the functional elements for constructing

logic

•

IOBs provide the interface between the package pins

and the CLBs

CLBs

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

VersaRing

IOBs

DLL

The Virtex architecture also includes the following circuits

that connect to the GRM.

vao_b.eps

•

Dedicated block memories of 4096 bits each

Figure 1: Virtex Architecture Overview

Clock DLLs for clock-distribution delay compensation

and clock domain control

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. Two

forms of over-voltage protection are provided, one that per-

mits 5 V compliance, and one that does not. For 5 V compli-

ance, a Zener-like structure connected to ground turns on

when the output rises to approximately 6.5 V. When PCI

3.3 V compliance is required, a conventional clamp diode is

•

3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing

resources

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

connected to the output supply voltage, V_CCO

Input/Output Block

The Virtex IOB, Figure 2, features SelectIO™ inputs and

outputs that support a wide variety of I/O signalling stan-

dards, see Table 1.

Optional pull-up and pull-down resistors and an optional

weak-keeper circuit are attached to each pad. Prior to con-

figuration, all pins not involved in configuration are forced

into their high-impedance state. The pull-down resistors and

the weak-keeper circuits are inactive, but inputs can option-

ally be pulled up.

The three IOB storage elements function either as edge-trig-

gered D-type flip-flops or as level sensitive latches. Each

IOB has a clock signal (CLK) shared by the three flip-flops

and independent clock enable signals for each flip-flop.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins will float.

Consequently, external pull-up or pull-down resistors must

be provided on pins required to be at a well-defined logic

level prior to configuration.

In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). For each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

All Virtex IOBs support IEEE 1149.1-compatible boundary

scan testing.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS003-2 (v2.8.1) December 9, 2002

Product Specification

www.xilinx.com

1-800-255-7778

Module 2 of 4

1 2 3 456 7 8...76

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与XCV1000-4BGG560I相关器件

型号	品牌	获取价格	描述	数据表
XCV1000-4FG680C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-4FG680I	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5BG560C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5BG560I	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5BGG560C	XILINX	获取价格	Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560
XCV1000-5BGG560I	XILINX	获取价格	Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560
XCV1000-5FG680C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5FG680I	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-6BG560C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-6BG560I	XILINX	获取价格	Field Programmable Gate Arrays

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