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XCV1000-4BGG560I

更新时间: 2024-02-09 22:28:05
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
76页 530K
描述
Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 250MHz, CMOS, PBGA560, BGA-560

XCV1000-4BGG560I 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:560
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.8最大时钟频率:250 MHz
CLB-Max的组合延迟:0.8 nsJESD-30 代码:S-PBGA-B560
JESD-609代码:e1长度:42.5 mm
湿度敏感等级:3可配置逻辑块数量:6144
等效关口数量:1124022端子数量:560
组织:6144 CLBS, 1124022 GATES封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):260
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:1.7 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:42.5 mm
Base Number Matches:1

XCV1000-4BGG560I 数据手册

 浏览型号XCV1000-4BGG560I的Datasheet PDF文件第2页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第3页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第4页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第6页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第7页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第8页 
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Virtex™ 2.5 V  
Field Programmable Gate Arrays  
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0
DS003-2 (v2.8.1) December 9, 2002  
Product Specification  
The output buffer and all of the IOB control signals have  
independent polarity controls.  
Architectural Description  
Virtex Array  
The Virtex user-programmable gate array, shown in  
Figure 1, comprises two major configurable elements: con-  
figurable logic blocks (CLBs) and input/output blocks  
(IOBs).  
DLL  
IOBs  
DLL  
VersaRing  
CLBs provide the functional elements for constructing  
logic  
IOBs provide the interface between the package pins  
and the CLBs  
CLBs  
CLBs interconnect through a general routing matrix (GRM).  
The GRM comprises an array of routing switches located at  
the intersections of horizontal and vertical routing channels.  
Each CLB nests into a VersaBlockthat also provides local  
routing resources to connect the CLB to the GRM.  
The VersaRingI/O interface provides additional routing  
resources around the periphery of the device. This routing  
improves I/O routability and facilitates pin locking.  
VersaRing  
IOBs  
DLL  
DLL  
The Virtex architecture also includes the following circuits  
that connect to the GRM.  
vao_b.eps  
Dedicated block memories of 4096 bits each  
Figure 1: Virtex Architecture Overview  
Clock DLLs for clock-distribution delay compensation  
and clock domain control  
All pads are protected against damage from electrostatic  
discharge (ESD) and from over-voltage transients. Two  
forms of over-voltage protection are provided, one that per-  
mits 5 V compliance, and one that does not. For 5 V compli-  
ance, a Zener-like structure connected to ground turns on  
when the output rises to approximately 6.5 V. When PCI  
3.3 V compliance is required, a conventional clamp diode is  
3-State buffers (BUFTs) associated with each CLB that  
drive dedicated segmentable horizontal routing  
resources  
Values stored in static memory cells control the configurable  
logic elements and interconnect resources. These values  
load into the memory cells on power-up, and can reload if  
necessary to change the function of the device.  
connected to the output supply voltage, VCCO  
.
Input/Output Block  
The Virtex IOB, Figure 2, features SelectIOinputs and  
outputs that support a wide variety of I/O signalling stan-  
dards, see Table 1.  
Optional pull-up and pull-down resistors and an optional  
weak-keeper circuit are attached to each pad. Prior to con-  
figuration, all pins not involved in configuration are forced  
into their high-impedance state. The pull-down resistors and  
the weak-keeper circuits are inactive, but inputs can option-  
ally be pulled up.  
The three IOB storage elements function either as edge-trig-  
gered D-type flip-flops or as level sensitive latches. Each  
IOB has a clock signal (CLK) shared by the three flip-flops  
and independent clock enable signals for each flip-flop.  
The activation of pull-up resistors prior to configuration is  
controlled on a global basis by the configuration mode pins.  
If the pull-up resistors are not activated, all the pins will float.  
Consequently, external pull-up or pull-down resistors must  
be provided on pins required to be at a well-defined logic  
level prior to configuration.  
In addition to the CLK and CE control signals, the three  
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-  
nal can be independently configured as a synchronous Set,  
a synchronous Reset, an asynchronous Preset, or an asyn-  
chronous Clear.  
All Virtex IOBs support IEEE 1149.1-compatible boundary  
scan testing.  
© 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS003-2 (v2.8.1) December 9, 2002  
Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 2 of 4  
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