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XCV1000-4BGG560I

更新时间： 2024-01-10 05:09:00
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
76页 530K
描述
Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 250MHz, CMOS, PBGA560, BGA-560

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XCV1000-4BGG560I 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：560
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.8最大时钟频率：250 MHz
CLB-Max的组合延迟：0.8 nsJESD-30 代码：S-PBGA-B560
JESD-609代码：e1长度：42.5 mm
湿度敏感等级：3可配置逻辑块数量：6144
等效关口数量：1124022端子数量：560
组织：6144 CLBS, 1124022 GATES封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：260
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：1.7 mm最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
端子面层：Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：42.5 mm
Base Number Matches：1

XCV1000-4BGG560I 数据手册

 浏览型号XCV1000-4BGG560I的Datasheet PDF文件第70页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第71页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第72页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第73页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第74页浏览型号XCV1000-4BGG560I的Datasheet PDF文件第75页 
R
Virtex™ 2.5 V Field Programmable Gate Arrays  
Revision History  
Date  
11/98  
01/99  
02/99  
05/99  
05/99  
07/99  
Version  
1.0  
Revision  
Initial Xilinx release.  
1.2  
Updated package drawings and specs.  
1.3  
Update of package drawings, updated specifications.  
Addition of package drawings and specifications.  
Replaced FG 676 & FG680 package drawings.  
1.4  
1.5  
1.6  
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit  
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O  
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and  
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and  
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.  
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated  
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.  
Added IOB Input Switching Characteristics Standard Adjustments.  
09/99  
01/00  
01/00  
03/00  
1.7  
1.8  
1.9  
2.0  
Speed grade update to preliminary status, Power-on specification and Clock-to-Out  
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and  
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE  
.
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,  
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions  
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.  
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement  
Methodology table for different I/O standards, changed buffered Hex line info and  
Input/Output Timing measurement notes.  
New TBCKO values; corrected FG680 package connection drawing; new note about status  
of CCLK pin after configuration.  
05/00  
05/00  
09/00  
2.1  
2.2  
2.3  
Modified "Pins not listed ..." statement. Speed grade update to Final status.  
Modified Table 18.  
•
Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.  
Corrected Units column in table under IOB Input Switching Characteristics.  
Added values to table under CLB SelectRAM Switching Characteristics.  
Corrected pinout info for devices in the BG256, BG432, and BG560 pkgs in Table 18.  
Corrected BG256 Pin Function Diagram.  
Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL.  
Converted file to modularized format. See section Virtex Data Sheet, below.  
Corrected pinout information for FG676 device in Table 4. (Added AB22 pin.)  
•
•
•
•
•
•
•
10/00  
2.4  
2.5  
04/02/01  
04/19/01  
07/19/01  
2.6  
2.7  
•
•
•
Clarified VCCINT pinout information and added AE19 pin for BG352 devices in Table 3.  
Changed pinouts listed for BG352 XCV400 devices in banks 0 thru 7.  
Changed pinouts listed for GND in TQ144 devices (see Table 2).  
07/19/02  
2.8  
Virtex Data Sheet  
The Virtex Data Sheet contains the following modules:  
•
DS003-1, Virtex 2.5V FPGAs:  
Introduction and Ordering Information (Module 1)  
•
•
DS003-3, Virtex 2.5V FPGAs:  
DC and Switching Characteristics (Module 3)  
•
DS003-2, Virtex 2.5V FPGAs:  
Functional Description (Module 2)  
DS003-4, Virtex 2.5V FPGAs:  
Pinout Tables (Module 4)  
Module 4 of 4  
28  
www.xilinx.com  
1-800-255-7778  
DS003-4 (v2.8) July 19, 2002  
Production Product Specification  
1...73747576

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XCV1000-5BGG560C XILINX Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560

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XCV1000-5BGG560I XILINX Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560

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