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XCV1000E-6FG900I

更新时间： 2024-02-24 01:05:57
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赛灵思 - XILINX 现场可编程门阵列可编程逻辑栅时钟
页数 文件大小 规格书
5页 89K
描述
Virtex-E 1.8 V Field Programmable Gate Arrays

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XCV1000E-6FG900I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：FBGA-900针数：900
Reach Compliance Code：not_compliantECCN代码：3A991.D
HTS代码：8542.39.00.01风险等级：5.78
Is Samacsys：N最大时钟频率：357 MHz
CLB-Max的组合延迟：0.47 nsJESD-30 代码：S-PBGA-B900
JESD-609代码：e0长度：31 mm
湿度敏感等级：3可配置逻辑块数量：6144
等效关口数量：331776输入次数：660
逻辑单元数量：27648输出次数：660
端子数量：900组织：6144 CLBS, 331776 GATES
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA900,30X30,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
电源：1.2/3.6,1.8 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.6 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：31 mm
Base Number Matches：1

XCV1000E-6FG900I 数据手册

 浏览型号XCV1000E-6FG900I的Datasheet PDF文件第2页浏览型号XCV1000E-6FG900I的Datasheet PDF文件第3页浏览型号XCV1000E-6FG900I的Datasheet PDF文件第4页浏览型号XCV1000E-6FG900I的Datasheet PDF文件第5页 
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Virtex™-E 1.8 V  
Field Programmable Gate Arrays  
0
0
DS022-1 (v2.2) November 9, 2001  
Preliminary Product Specification  
Features  
•
Fast, High-Density 1.8 V FPGA Family  
•
High-Performance Built-In Clock Management Circuitry  
-
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Densities from 58 k to 4 M system gates  
-
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Eight fully digital Delay-Locked Loops (DLLs)  
130 MHz internal performance (four LUT levels)  
Designed for low-power operation  
Digitally-Synthesized 50% duty cycle for Double  
Data Rate (DDR) Applications  
-
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Clock Multiply and Divide  
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz  
Zero-delay conversion of high-speed LVPECL/LVDS  
clocks to any I/O standard  
•
•
Highly Flexible SelectI/O+™ Technology  
-
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Supports 20 high-performance interface standards  
•
Flexible Architecture Balances Speed and Density  
Up to 804 singled-ended I/Os or 344 differential I/O  
pairs for an aggregate bandwidth of > 100 Gb/s  
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Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
Differential Signalling Support  
Cascade chain for wide-input function  
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LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL  
Differential I/O signals can be input, output, or I/O  
Compatible with standard differential devices  
Abundant registers/latches with clock enable, and  
dual synchronous/asynchronous set and reset  
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-
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Internal 3-state bussing  
LVPECL and LVDS clock inputs for 300+ MHz  
clocks  
IEEE 1149.1 boundary-scan logic  
Die-temperature sensor diode  
•
•
Proprietary High-Performance SelectLink™  
Technology  
•
Supported by Xilinx Foundation™ and Alliance Series™  
Development Systems  
-
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Double Data Rate (DDR) to Virtex-E link  
Web-based HDL generation methodology  
-
-
Further compile time reduction of 50%  
Internet Team Design (ITD) tool ideal for  
million-plus gate density designs  
Sophisticated SelectRAM+™ Memory Hierarchy  
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1 Mb of internal configurable distributed RAM  
Up to 832 Kb of synchronous internal block RAM  
True Dual-Port™ BlockRAM capability  
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Wide selection of PC and workstation platforms  
•
•
SRAM-Based In-System Configuration  
Unlimited re-programmability  
Advanced Packaging Options  
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Memory bandwidth up to 1.66 Tb/s (equivalent  
bandwidth of over 100 RAMBUS channels)  
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0.8 mm Chip-scale  
1.0 mm BGA  
1.27 mm BGA  
HQ/PQ  
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Designed for high-performance Interfaces to  
External Memories  
-
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200 MHz ZBT* SRAMs  
200 Mb/s DDR SDRAMs  
Supported by free Synthesizable reference design  
•
•
0.18 m 6-Layer Metal Process  
100% Factory Tested  
* ZBT is a trademark of Integrated Device Technology, Inc.  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS022-1 (v2.2) November 9, 2001  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
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