5秒后页面跳转
XCV1000E-6FGG860C PDF预览

XCV1000E-6FGG860C

更新时间: 2024-01-03 09:19:43
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
54页 581K
描述
Field Programmable Gate Array, 6144 CLBs, 331776 Gates, 357MHz, 27648-Cell, CMOS, PBGA860, FBGA-860

XCV1000E-6FGG860C 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA860,42X42,40针数:860
Reach Compliance Code:compliantECCN代码:3A001.A.7.A
HTS代码:8542.39.00.01风险等级:5.79
最大时钟频率:357 MHzCLB-Max的组合延迟:0.47 ns
JESD-30 代码:S-PBGA-B860JESD-609代码:e1
长度:42.5 mm湿度敏感等级:3
可配置逻辑块数量:6144等效关口数量:331776
输入次数:660逻辑单元数量:27648
输出次数:660端子数量:860
最高工作温度:85 °C最低工作温度:
组织:6144 CLBS, 331776 GATES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA860,42X42,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):245电源:1.2/3.6,1.8 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2.2 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:42.5 mm
Base Number Matches:1

XCV1000E-6FGG860C 数据手册

 浏览型号XCV1000E-6FGG860C的Datasheet PDF文件第2页浏览型号XCV1000E-6FGG860C的Datasheet PDF文件第3页浏览型号XCV1000E-6FGG860C的Datasheet PDF文件第4页浏览型号XCV1000E-6FGG860C的Datasheet PDF文件第5页浏览型号XCV1000E-6FGG860C的Datasheet PDF文件第6页浏览型号XCV1000E-6FGG860C的Datasheet PDF文件第7页 
0
R
Virtex™-E 1.8 V  
Field Programmable Gate Arrays  
0
0
DS022-2 (v2.8) January 16, 2006  
Production Product Specification  
Architectural Description  
Virtex-E Array  
The Virtex-E user-programmable gate array, shown in  
Figure 1, comprises two major configurable elements: con-  
figurable logic blocks (CLBs) and input/output blocks (IOBs).  
Values stored in static memory cells control the configurable  
logic elements and interconnect resources. These values  
load into the memory cells on power-up, and can reload if  
necessary to change the function of the device.  
CLBs provide the functional elements for constructing  
logic  
Input/Output Block  
The Virtex-E IOB, Figure 2, features SelectI/O+ inputs and  
outputs that support a wide variety of I/O signalling stan-  
dards, see Table 1.  
IOBs provide the interface between the package pins  
and the CLBs  
CLBs interconnect through a general routing matrix (GRM).  
The GRM comprises an array of routing switches located at  
the intersections of horizontal and vertical routing channels.  
Each CLB nests into a VersaBlock™ that also provides local  
routing resources to connect the CLB to the GRM.  
Q
D
CE  
T
TCE  
Weak  
Keeper  
SR  
PAD  
DLLDLL  
DLLDLL  
O
Q
D
CE  
OCE  
OBUFT  
VersaRing  
SR  
I
IQ  
Programmable  
Delay  
Q
D
CE  
IBUF  
Vref  
SR  
SR  
CLK  
ICE  
ds022_02_091300  
Figure 2: Virtex-E Input/Output Block (IOB)  
The three IOB storage elements function either as  
edge-triggered D-type flip-flops or as level-sensitive latches.  
Each IOB has a clock signal (CLK) shared by the three  
flip-flops and independent clock enable signals for each  
flip-flop.  
VersaRing  
DLLDLL  
DLLDLL  
ds022_01_121099  
Figure 1: Virtex-E Architecture Overview  
The VersaRing™ I/O interface provides additional routing  
resources around the periphery of the device. This routing  
improves I/O routability and facilitates pin locking.  
The Virtex-E architecture also includes the following circuits  
that connect to the GRM.  
Dedicated block memories of 4096 bits each  
Clock DLLs for clock-distribution delay compensation  
and clock domain control  
3-State buffers (BUFTs) associated with each CLB that  
drive dedicated segmentable horizontal routing  
resources  
© 2000–2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS022-2 (v2.8) January 16, 2006  
Production Product Specification  
www.xilinx.com  
Module 2 of 4  
1

与XCV1000E-6FGG860C相关器件

型号 品牌 描述 获取价格 数据表
XCV1000E-6HQ240C XILINX Virtex-E 1.8 V Field Programmable Gate Arrays

获取价格

XCV1000E-6HQ240I XILINX Virtex-E 1.8 V Field Programmable Gate Arrays

获取价格

XCV1000E-6HQG240I XILINX Field Programmable Gate Array, 27648-Cell, CMOS, PQFP240

获取价格

XCV1000E-7BG240C XILINX Virtex-E 1.8 V Field Programmable Gate Arrays

获取价格

XCV1000E-7BG240I XILINX Virtex-E 1.8 V Field Programmable Gate Arrays

获取价格

XCV1000E-7BG560C XILINX Virtex-E 1.8 V Field Programmable Gate Arrays

获取价格