Datasheet > XCV1000-4BGG560I

XCV1000-4BGG560I

更新时间： 2024-02-28 05:08:17

品牌	Logo	应用领域
赛灵思 - XILINX		时钟栅可编程逻辑
页数	文件大小	规格书
76页	530K
描述
Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 250MHz, CMOS, PBGA560, BGA-560

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XCV1000-4BGG560I 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	560
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.8	最大时钟频率：	250 MHz
CLB-Max的组合延迟：	0.8 ns	JESD-30 代码：	S-PBGA-B560
JESD-609代码：	e1	长度：	42.5 mm
湿度敏感等级：	3	可配置逻辑块数量：	6144
等效关口数量：	1124022	端子数量：	560
组织：	6144 CLBS, 1124022 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	260
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压：	2.625 V
最小供电电压：	2.375 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
端子面层：	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	42.5 mm
Base Number Matches：	1

XCV1000-4BGG560I 数据手册

浏览型号XCV1000-4BGG560I的Datasheet PDF文件第10页

Virtex™ 2.5 V Field Programmable Gate Arrays

Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in Figure 3. Each bank has

multiple V_CCOpins, all of which must be connected to the

same voltage. This voltage is determined by the output

standards in use.

Input Path

A buffer In the Virtex IOB input path routes the input signal

either directly to internal logic or through an optional input

flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Bank 0

Bank 1

GCLK3 GCLK2

Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold voltage, V_REF. The need to supply V_REFimposes

constraints on which standards can used in close proximity

to each other. See I/O Banking, page 3.

Virtex

Device

GCLK1 GCLK0

There are optional pull-up and pull-down resistors at each

user I/O input for use after configuration. Their value is in

the range 50 kΩ – 100 kΩ.

Bank 5

Bank 4

X8778_b

Output Path

Figure 3: Virtex I/O Banks

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

Within a bank, output standards can be mixed only if they

use the same V_CCO. Compatible standards are shown in

Table 2. GTL and GTL+ appear under all voltages because

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

their open-drain outputs do not depend on V_CCO

Table 2: Compatible Output Standards

V_CCOCompatible Standards

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48mA. Drive

strength and slew rate controls minimize bus transients.

3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+

2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+

1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+

In most signalling standards, the output High voltage

depends on an externally supplied V_CCOvoltage. The need

to supply V_CCOimposes constraints on which standards

can be used in close proximity to each other. See I/O Bank-

ing, page 3.

Some input standards require a user-supplied threshold

voltage, V_REF. In this case, certain user-I/O pins are auto-

matically configured as inputs for the V_REFvoltage. Approx-

imately one in six of the I/O pins in the bank assume this

role.

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

The V_REFpins within a bank are interconnected internally

and consequently only one V_REFvoltage can be used within

each bank. All V_REFpins in the bank, however, must be con-

nected to the external voltage source for correct operation.

Because the weak-keeper circuit uses the IOB input buffer

to monitor the input level, an appropriate V_REFvoltage must

be provided if the signalling standard requires one. The pro-

vision of this voltage must comply with the I/O banking

rules.

Within a bank, inputs that require V_REFcan be mixed with

those that do not. However, only one V_REFvoltage can be

used within a bank. Input buffers that use V_REFare not 5 V

tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V

tolerant.

I/O Banking

The V_CCOand V_REFpins for each bank appear in the device

Pinout tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

Some of the I/O standards described above require V_CCO

and/or V_REFvoltages. These voltages externally and con-

nected to device pins that serve groups of IOBs, called

banks. Consequently, restrictions exist about which I/O

standards can be combined within a given bank.

Within a given package, the number of V_REFand V_CCOpins

can vary depending on the size of device. In larger devices,

DS003-2 (v2.8.1) December 9, 2002

Product Specification

www.xilinx.com

1-800-255-7778

Module 2 of 4

1...4 5 678 9 10...76

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与XCV1000-4BGG560I相关器件

型号	品牌	获取价格	描述	数据表
XCV1000-4FG680C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-4FG680I	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5BG560C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5BG560I	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5BGG560C	XILINX	获取价格	Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560
XCV1000-5BGG560I	XILINX	获取价格	Field Programmable Gate Array, 6144 CLBs, 1124022 Gates, 294MHz, CMOS, PBGA560, BGA-560
XCV1000-5FG680C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-5FG680I	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-6BG560C	XILINX	获取价格	Field Programmable Gate Arrays
XCV1000-6BG560I	XILINX	获取价格	Field Programmable Gate Arrays

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