APPLICATION NOTE
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CoolRunner™ XPLA3 CPLD
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14*
DS012 (v1.1) March 3, 2000
Advance Product Specification
Features
Family Overview
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Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
Innovative XPLA3 architecture combines high speed
with extreme flexibility
Based on industry's first TotalCMOS™ PLD - both
CMOS design and process technologies
Advanced 0.35µ five metal layer E2CMOS process
The CoolRunner XPLA3 (eXtended Programmable Logic
Array) family of CPLDs is targeted for low power systems
that include portable, handheld, and power sensitive appli-
cations. Each member of the XPLA3 family includes Fast
Zero Power (FZP) design technology that combines low
power and high speed. With this design technique, the
XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while
simultaneously delivering power that is less than 100 µA at
standby without the need for "turbo bits" or other power
down schemes. By replacing conventional sense amplifier
methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cas-
caded chain of pure CMOS gates, the dynamic power is
also substantially lower than any competing CPLD. Cool-
Runner devices are the only TotalCMOS PLDs, as they use
both a CMOS process technology and the patented full
CMOS FZP design technique.
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1,000 erase/program cycles guaranteed
20 years data retention guaranteed
3V, In-System Programmable (ISP) using JTAG IEEE
1149.1 interface
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Full Boundary Scan Test (IEEE 1149.1)
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Ultra-low static power of less than 100 µA
Simple deterministic timing model
Support for complex asynchronous clocking
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16 product term clocks and four local control term
clocks per logic block
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Four global clocks and one universal control term
clock per device
To the original XPLA architecture, XPLA3 adds a direct
input register path, multiple clocks (both dedicated and
product term generated), and both reset and preset for
each macrocell, with a full PLA structure. These enhance-
ments deliver high speed coupled with very flexible logic
allocation which results in the ability to make design
changes without changing pinout. The XPLA3 logic block
includes a pool of 48 product terms that can be allocated to
any macrocell in the logic block. Logic that is common to
multiple macrocells can be placed on a single PLA product
term and shared, effectively increasing design density.
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Excellent pin retention during design changes
5V tolerant I/O pins
Input register set up time of 1.7 ns
Logic expandable to 48 product terms
High-speed pin-to-pin delays of 5.0 ns
Slew rate control per macrocell
100% routable
Security bit prevents unauthorized access
Supports hot-plugging capability
Design entry/verification using Xilinx or industry
standard CAE tools
XPLA3 CPLDs are supported by WebPACK from Xilinx and
industry standard CAE tools (Cadence/OrCAD, Exemplar
Logic, Mentor, Synopsys, Viewlogic, andd Synplicity), using
text (ABEL, VHDL, Verilog) and schematic capture design
entry. Design verification uses industry standard simulators
for functional and timing simulation. Development is sup-
ported on personal computer, Sparc, and HP platforms.
Device fitting uses Xilinx developed tools including
WebFITTER.
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Innovative Control Term structure provides:
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Asynchronous macrocell clocking
Asynchronous macrocell register preset/reset
Clock enable control per macrocell
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Four output enable controls per logic block
Foldback NAND for synthesis optimization
Global 3-state which facilitates "bed of nails" testing
Available in Chip-scale BGA, and QFP packages
Commercial and extended voltage industrial grades
Pin compatible with existing CoolRunner low-power
family devices
The XPLA3 family features also include industry-standard,
IEEE 1149.1, JTAG interface through which In-System Pro-
gramming (ISP) and reprogramming of the device can
DS012 (v1.1) March 3, 2000
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